261 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,  in reg_update_bits()  function
576 	reg_update_bits(ldev->regs, LTDC_GCR,  in ltdc_crtc_mode_set_nofb()
581 	reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);  in ltdc_crtc_mode_set_nofb()
585 	reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);  in ltdc_crtc_mode_set_nofb()
589 	reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);  in ltdc_crtc_mode_set_nofb()
593 	reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);  in ltdc_crtc_mode_set_nofb()
785 	reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,  in ltdc_plane_atomic_update()
790 	reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,  in ltdc_plane_atomic_update()
804 	reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);  in ltdc_plane_atomic_update()
811 	reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,  in ltdc_plane_atomic_update()
816 	reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);  in ltdc_plane_atomic_update()
828 	reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,  in ltdc_plane_atomic_update()
833 	reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);  in ltdc_plane_atomic_update()
844 	reg_update_bits(ldev->regs, LTDC_L1CR + lofs,  in ltdc_plane_atomic_update()