23 #define HDA_ANA_CFG                     0x0000
24 #define HDA_ANA_SCALE_CTRL_Y            0x0004
25 #define HDA_ANA_SCALE_CTRL_CB           0x0008
26 #define HDA_ANA_SCALE_CTRL_CR           0x000C
27 #define HDA_ANA_ANC_CTRL                0x0010
28 #define HDA_ANA_SRC_Y_CFG               0x0014
29 #define HDA_COEFF_Y_PH1_TAP123          0x0018
30 #define HDA_COEFF_Y_PH1_TAP456          0x001C
31 #define HDA_COEFF_Y_PH2_TAP123          0x0020
32 #define HDA_COEFF_Y_PH2_TAP456          0x0024
33 #define HDA_COEFF_Y_PH3_TAP123          0x0028
34 #define HDA_COEFF_Y_PH3_TAP456          0x002C
35 #define HDA_COEFF_Y_PH4_TAP123          0x0030
36 #define HDA_COEFF_Y_PH4_TAP456          0x0034
37 #define HDA_ANA_SRC_C_CFG               0x0040
38 #define HDA_COEFF_C_PH1_TAP123          0x0044
39 #define HDA_COEFF_C_PH1_TAP456          0x0048
40 #define HDA_COEFF_C_PH2_TAP123          0x004C
41 #define HDA_COEFF_C_PH2_TAP456          0x0050
42 #define HDA_COEFF_C_PH3_TAP123          0x0054
43 #define HDA_COEFF_C_PH3_TAP456          0x0058
44 #define HDA_COEFF_C_PH4_TAP123          0x005C
45 #define HDA_COEFF_C_PH4_TAP456          0x0060
46 #define HDA_SYNC_AWGI                   0x0300
49 #define CFG_AWG_ASYNC_EN                BIT(0)
54 #define CFG_AWG_FLTR_MODE_MASK          (0xF << CFG_AWG_FLTR_MODE_SHIFT)
55 #define CFG_AWG_FLTR_MODE_SD            (0 << CFG_AWG_FLTR_MODE_SHIFT)
61 #define CFG_PBPR_SYNC_OFF_MASK          (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
62 #define CFG_PBPR_SYNC_OFF_VAL           0x117 /* Voltage dependent. stiH416 */
65 #define SCALE_CTRL_Y_DFLT               0x00C50256
66 #define SCALE_CTRL_CB_DFLT              0x00DB0249
67 #define SCALE_CTRL_CR_DFLT              0x00DB0249
74 #define HDA_ANA_SRC_Y_CFG_ALT_2X        0x01130000
76 	0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
77 	0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
80 #define HDA_ANA_SRC_C_CFG_ALT_2X        0x01750004
82 	0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
83 	0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
87 #define HDA_ANA_SRC_Y_CFG_4X            0x01ED0005
88 #define HDA_ANA_SRC_C_CFG_4X            0x01ED0004
90 	0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
91 	0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
99 	0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
100 	0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
101 	0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
102 	0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
103 	0x00000104, 0x00001AE8
110 	0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
111 	0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
112 	0x00000C44, 0x00000104, 0x00001804, 0x00000971,
113 	0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
114 	0x00000104, 0x00001AE8
121 	0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
122 	0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
123 	0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
124 	0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
125 	0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
126 	0x00001C52
133 	0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
134 	0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
135 	0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
136 	0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
137 	0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
138 	0x00001C52
145 	0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
146 	0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
147 	0x00000E50, 0x00000104, 0x00001804, 0x00000971,
148 	0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
149 	0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
150 	0x00001C52
157 	0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
158 	0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
184 		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
189 		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
194 		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
199 		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
204 		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
208 	{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
209 		   1430, 1650, 0, 720, 725, 730, 750, 0,
213 	{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
214 		   1430, 1650, 0, 720, 725, 730, 750, 0,
218 	{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
219 		   1760, 1980, 0, 720, 725, 730, 750, 0,
224 		   798, 858, 0, 480, 489, 495, 525, 0,
229 		   798, 858, 0, 480, 489, 495, 525, 0,
286 	for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)  in hda_get_mode_idx()
315 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
329 	for (i = 0; i < AWG_MAX_INST; i++) {  in hda_dbg_awg_microcode()
330 		if (i % 8 == 0)  in hda_dbg_awg_microcode()
340 	seq_printf(s, "\n\n  %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);  in hda_dbg_video_dacs_ctrl()
350 	seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs);  in hda_dbg_show()
363 	return 0;  in hda_dbg_show()
367 	{ "hda", hda_dbg_show, 0, NULL },
374 	for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++)  in hda_debugfs_init()
395 	for (i = 0; i < nb; i++)  in sti_hda_configure_awg()
398 		hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);  in sti_hda_configure_awg()
415 	hda_write(hda, 0, HDA_ANA_ANC_CTRL);  in sti_hda_disable()
490 	for (i = 0; i < SAMPLER_COEF_NB; i++) {  in sti_hda_pre_enable()
496 	val = 0;  in sti_hda_pre_enable()
498 	    0 : CFG_AWG_ASYNC_VSYNC_MTD;  in sti_hda_pre_enable()
549 	if (ret < 0)  in sti_hda_set_mode()
555 	if (ret < 0)  in sti_hda_set_mode()
576 	int count = 0;  in sti_hda_connector_get_modes()
583 	for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {  in sti_hda_connector_get_modes()
591 		if (i == 0)  in sti_hda_connector_get_modes()
647 	return 0;  in sti_hda_late_register()
700 	drm_bridge_attach(encoder, bridge, NULL, 0);  in sti_hda_bind()
722 	return 0;  in sti_hda_bind()
796 	return 0;  in sti_hda_remove()