Lines Matching +full:5 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Sandy Huang <hjc@rock-chips.com>
6 * Mark Yao <mark.yao@rock-chips.com>
13 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
14 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
15 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
16 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
17 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
18 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
19 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
20 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
23 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
24 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
25 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3)
26 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2)
27 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1)
28 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)
31 #define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7)
32 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6)
33 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5)
34 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4)
35 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3)
36 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2)
37 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1)
38 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)
44 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5)
45 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4)
46 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3)
47 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2)
48 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1)
49 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
52 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5)
53 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4)
54 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3)
55 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2)
56 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1)
57 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)
80 (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
86 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3)
89 #define LVDS_MSB BIT(3)
90 #define LVDS_DUAL BIT(4)
91 #define LVDS_FMT_1 BIT(5)
92 #define LVDS_TTL_EN BIT(6)
93 #define LVDS_START_PHASE_RST_1 BIT(7)
94 #define LVDS_DCLK_INV BIT(8)
95 #define LVDS_CH0_EN BIT(11)
96 #define LVDS_CH1_EN BIT(12)
97 #define LVDS_PWRDN BIT(15)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)