Lines Matching full:hdmi
38 /* need to be unset if hdmi or i2c should control voltage */
58 * @lcdsel_big: reg value of selecting vop big for HDMI
59 * @lcdsel_lit: reg value of selecting vop little for HDMI
74 struct dw_hdmi *hdmi; member
189 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
191 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
193 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
194 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
195 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
196 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
199 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
200 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
201 hdmi->vpll_clk = NULL; in rockchip_hdmi_parse_dt()
202 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
204 } else if (IS_ERR(hdmi->vpll_clk)) { in rockchip_hdmi_parse_dt()
205 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
206 return PTR_ERR(hdmi->vpll_clk); in rockchip_hdmi_parse_dt()
209 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); in rockchip_hdmi_parse_dt()
210 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
211 hdmi->grf_clk = NULL; in rockchip_hdmi_parse_dt()
212 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
214 } else if (IS_ERR(hdmi->grf_clk)) { in rockchip_hdmi_parse_dt()
215 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
216 return PTR_ERR(hdmi->grf_clk); in rockchip_hdmi_parse_dt()
223 dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, in dw_hdmi_rockchip_mode_valid() argument
258 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_mode_set() local
260 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); in dw_hdmi_rockchip_encoder_mode_set()
265 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_enable() local
269 if (hdmi->chip_data->lcdsel_grf_reg < 0) in dw_hdmi_rockchip_encoder_enable()
272 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); in dw_hdmi_rockchip_encoder_enable()
274 val = hdmi->chip_data->lcdsel_lit; in dw_hdmi_rockchip_encoder_enable()
276 val = hdmi->chip_data->lcdsel_big; in dw_hdmi_rockchip_encoder_enable()
278 ret = clk_prepare_enable(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
280 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
284 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); in dw_hdmi_rockchip_encoder_enable()
286 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
288 clk_disable_unprepare(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
289 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", in dw_hdmi_rockchip_encoder_enable()
318 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_genphy_init() local
320 return phy_power_on(hdmi->phy); in dw_hdmi_rockchip_genphy_init()
325 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_genphy_disable() local
327 phy_power_off(hdmi->phy); in dw_hdmi_rockchip_genphy_disable()
332 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3228_setup_hpd() local
336 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
343 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
352 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3328_read_hpd() local
358 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
363 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
372 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3328_setup_hpd() local
377 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
382 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
387 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
471 { .compatible = "rockchip,rk3228-dw-hdmi",
474 { .compatible = "rockchip,rk3288-dw-hdmi",
477 { .compatible = "rockchip,rk3328-dw-hdmi",
480 { .compatible = "rockchip,rk3399-dw-hdmi",
495 struct rockchip_hdmi *hdmi; in dw_hdmi_rockchip_bind() local
501 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in dw_hdmi_rockchip_bind()
502 if (!hdmi) in dw_hdmi_rockchip_bind()
511 hdmi->dev = &pdev->dev; in dw_hdmi_rockchip_bind()
512 hdmi->chip_data = plat_data->phy_data; in dw_hdmi_rockchip_bind()
513 plat_data->phy_data = hdmi; in dw_hdmi_rockchip_bind()
514 encoder = &hdmi->encoder; in dw_hdmi_rockchip_bind()
526 ret = rockchip_hdmi_parse_dt(hdmi); in dw_hdmi_rockchip_bind()
528 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n"); in dw_hdmi_rockchip_bind()
532 ret = clk_prepare_enable(hdmi->vpll_clk); in dw_hdmi_rockchip_bind()
534 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", in dw_hdmi_rockchip_bind()
539 hdmi->phy = devm_phy_optional_get(dev, "hdmi"); in dw_hdmi_rockchip_bind()
540 if (IS_ERR(hdmi->phy)) { in dw_hdmi_rockchip_bind()
541 ret = PTR_ERR(hdmi->phy); in dw_hdmi_rockchip_bind()
543 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); in dw_hdmi_rockchip_bind()
550 platform_set_drvdata(pdev, hdmi); in dw_hdmi_rockchip_bind()
552 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); in dw_hdmi_rockchip_bind()
558 if (IS_ERR(hdmi->hdmi)) { in dw_hdmi_rockchip_bind()
559 ret = PTR_ERR(hdmi->hdmi); in dw_hdmi_rockchip_bind()
561 clk_disable_unprepare(hdmi->vpll_clk); in dw_hdmi_rockchip_bind()
570 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_unbind() local
572 dw_hdmi_unbind(hdmi->hdmi); in dw_hdmi_rockchip_unbind()
573 clk_disable_unprepare(hdmi->vpll_clk); in dw_hdmi_rockchip_unbind()
595 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_resume() local
597 dw_hdmi_resume(hdmi->hdmi); in dw_hdmi_rockchip_resume()