393 		DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_phy_init()
401 		DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");  in dw_mipi_dsi_phy_init()
492 		DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);  in dw_mipi_dsi_phy_power_on()
527 		DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_get_lane_mbps()
540 			DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_get_lane_mbps()
603 		DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");  in dw_mipi_dsi_get_lane_mbps()
766 		DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);  in dw_mipi_dsi_encoder_enable()
894 			DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");  in dw_mipi_dsi_rockchip_bind()
899 			DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");  in dw_mipi_dsi_rockchip_bind()
911 			DRM_DEV_ERROR(dev, "could not get slaves data\n");  in dw_mipi_dsi_rockchip_bind()
922 		DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);  in dw_mipi_dsi_rockchip_bind()
928 		DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");  in dw_mipi_dsi_rockchip_bind()
934 		DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);  in dw_mipi_dsi_rockchip_bind()
969 		DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",  in dw_mipi_dsi_rockchip_host_attach()
980 			DRM_DEV_ERROR(second,  in dw_mipi_dsi_rockchip_host_attach()
1027 		DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");  in dw_mipi_dsi_rockchip_probe()
1042 		DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);  in dw_mipi_dsi_rockchip_probe()
1050 		DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);  in dw_mipi_dsi_rockchip_probe()
1064 			DRM_DEV_ERROR(dev,  in dw_mipi_dsi_rockchip_probe()
1075 			DRM_DEV_ERROR(dev,  in dw_mipi_dsi_rockchip_probe()
1085 			DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);  in dw_mipi_dsi_rockchip_probe()
1092 		DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");  in dw_mipi_dsi_rockchip_probe()
1108 			DRM_DEV_ERROR(dev,  in dw_mipi_dsi_rockchip_probe()