310 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)  in dsi_write()  argument
312 	writel(val, dsi->base + reg);  in dsi_write()
315 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)  in dsi_read()  argument
317 	return readl(dsi->base + reg);  in dsi_read()
320 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)  in dsi_set()  argument
322 	dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);  in dsi_set()
325 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,  in dsi_update_bits()  argument
328 	dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);  in dsi_update_bits()
331 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,  in dw_mipi_dsi_phy_write()  argument
340 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);  in dw_mipi_dsi_phy_write()
342 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
345 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);  in dw_mipi_dsi_phy_write()
347 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
350 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);  in dw_mipi_dsi_phy_write()
356 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)  in ns2bc()  argument
358 	return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);  in ns2bc()
364 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)  in ns2ui()  argument
366 	return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);  in ns2ui()
371 	struct dw_mipi_dsi_rockchip *dsi = priv_data;  in dw_mipi_dsi_phy_init()  local
374 	if (dsi->phy)  in dw_mipi_dsi_phy_init()
389 	vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;  in dw_mipi_dsi_phy_init()
391 	i = max_mbps_to_parameter(dsi->lane_mbps);  in dw_mipi_dsi_phy_init()
393 		DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_phy_init()
395 			      dsi->lane_mbps);  in dw_mipi_dsi_phy_init()
399 	ret = clk_prepare_enable(dsi->phy_cfg_clk);  in dw_mipi_dsi_phy_init()
401 		DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");  in dw_mipi_dsi_phy_init()
405 	dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,  in dw_mipi_dsi_phy_init()
411 	dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,  in dw_mipi_dsi_phy_init()
413 	dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,  in dw_mipi_dsi_phy_init()
417 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,  in dw_mipi_dsi_phy_init()
420 	dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,  in dw_mipi_dsi_phy_init()
421 			      INPUT_DIVIDER(dsi->input_div));  in dw_mipi_dsi_phy_init()
422 	dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,  in dw_mipi_dsi_phy_init()
423 			      LOOP_DIV_LOW_SEL(dsi->feedback_div) |  in dw_mipi_dsi_phy_init()
431 	dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,  in dw_mipi_dsi_phy_init()
433 	dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,  in dw_mipi_dsi_phy_init()
434 			      LOOP_DIV_HIGH_SEL(dsi->feedback_div) |  in dw_mipi_dsi_phy_init()
436 	dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,  in dw_mipi_dsi_phy_init()
439 	dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,  in dw_mipi_dsi_phy_init()
441 	dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,  in dw_mipi_dsi_phy_init()
444 	dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,  in dw_mipi_dsi_phy_init()
448 	dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,  in dw_mipi_dsi_phy_init()
451 	dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,  in dw_mipi_dsi_phy_init()
456 	dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
457 			      TLP_PROGRAM_EN | ns2bc(dsi, 500));  in dw_mipi_dsi_phy_init()
458 	dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
459 			      THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));  in dw_mipi_dsi_phy_init()
460 	dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
461 			      THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));  in dw_mipi_dsi_phy_init()
462 	dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
463 			      THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));  in dw_mipi_dsi_phy_init()
464 	dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
465 			      BIT(5) | ns2bc(dsi, 100));  in dw_mipi_dsi_phy_init()
466 	dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
467 			      BIT(5) | (ns2bc(dsi, 60) + 7));  in dw_mipi_dsi_phy_init()
469 	dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
470 			      TLP_PROGRAM_EN | ns2bc(dsi, 500));  in dw_mipi_dsi_phy_init()
471 	dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
472 			      THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));  in dw_mipi_dsi_phy_init()
473 	dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
474 			      THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));  in dw_mipi_dsi_phy_init()
475 	dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
476 			      THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));  in dw_mipi_dsi_phy_init()
477 	dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,  in dw_mipi_dsi_phy_init()
478 			      BIT(5) | ns2bc(dsi, 100));  in dw_mipi_dsi_phy_init()
480 	clk_disable_unprepare(dsi->phy_cfg_clk);  in dw_mipi_dsi_phy_init()
487 	struct dw_mipi_dsi_rockchip *dsi = priv_data;  in dw_mipi_dsi_phy_power_on()  local
490 	ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);  in dw_mipi_dsi_phy_power_on()
492 		DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);  in dw_mipi_dsi_phy_power_on()
496 	phy_configure(dsi->phy, &dsi->phy_opts);  in dw_mipi_dsi_phy_power_on()
497 	phy_power_on(dsi->phy);  in dw_mipi_dsi_phy_power_on()
502 	struct dw_mipi_dsi_rockchip *dsi = priv_data;  in dw_mipi_dsi_phy_power_off()  local
504 	phy_power_off(dsi->phy);  in dw_mipi_dsi_phy_power_off()
512 	struct dw_mipi_dsi_rockchip *dsi = priv_data;  in dw_mipi_dsi_get_lane_mbps()  local
524 	dsi->format = format;  in dw_mipi_dsi_get_lane_mbps()
525 	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in dw_mipi_dsi_get_lane_mbps()
527 		DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_get_lane_mbps()
529 			      dsi->format);  in dw_mipi_dsi_get_lane_mbps()
540 			DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_get_lane_mbps()
545 	if (dsi->phy) {  in dw_mipi_dsi_get_lane_mbps()
548 						 &dsi->phy_opts.mipi_dphy);  in dw_mipi_dsi_get_lane_mbps()
549 		dsi->lane_mbps = target_mbps;  in dw_mipi_dsi_get_lane_mbps()
550 		*lane_mbps = dsi->lane_mbps;  in dw_mipi_dsi_get_lane_mbps()
555 	fin = clk_get_rate(dsi->pllref_clk);  in dw_mipi_dsi_get_lane_mbps()
598 		dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);  in dw_mipi_dsi_get_lane_mbps()
599 		*lane_mbps = dsi->lane_mbps;  in dw_mipi_dsi_get_lane_mbps()
600 		dsi->input_div = best_prediv;  in dw_mipi_dsi_get_lane_mbps()
601 		dsi->feedback_div = best_fbdiv;  in dw_mipi_dsi_get_lane_mbps()
603 		DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");  in dw_mipi_dsi_get_lane_mbps()
695 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,  in dw_mipi_dsi_rockchip_config()  argument
698 	if (dsi->cdata->lcdsel_grf_reg)  in dw_mipi_dsi_rockchip_config()
699 		regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,  in dw_mipi_dsi_rockchip_config()
700 			mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);  in dw_mipi_dsi_rockchip_config()
702 	if (dsi->cdata->lanecfg1_grf_reg)  in dw_mipi_dsi_rockchip_config()
703 		regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,  in dw_mipi_dsi_rockchip_config()
704 					      dsi->cdata->lanecfg1);  in dw_mipi_dsi_rockchip_config()
706 	if (dsi->cdata->lanecfg2_grf_reg)  in dw_mipi_dsi_rockchip_config()
707 		regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,  in dw_mipi_dsi_rockchip_config()
708 					      dsi->cdata->lanecfg2);  in dw_mipi_dsi_rockchip_config()
710 	if (dsi->cdata->enable_grf_reg)  in dw_mipi_dsi_rockchip_config()
711 		regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,  in dw_mipi_dsi_rockchip_config()
712 					      dsi->cdata->enable);  in dw_mipi_dsi_rockchip_config()
721 	struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);  in dw_mipi_dsi_encoder_atomic_check()  local
723 	switch (dsi->format) {  in dw_mipi_dsi_encoder_atomic_check()
739 	if (dsi->slave)  in dw_mipi_dsi_encoder_atomic_check()
747 	struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);  in dw_mipi_dsi_encoder_enable()  local
750 	mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,  in dw_mipi_dsi_encoder_enable()
751 						&dsi->encoder);  in dw_mipi_dsi_encoder_enable()
755 	pm_runtime_get_sync(dsi->dev);  in dw_mipi_dsi_encoder_enable()
756 	if (dsi->slave)  in dw_mipi_dsi_encoder_enable()
757 		pm_runtime_get_sync(dsi->slave->dev);  in dw_mipi_dsi_encoder_enable()
764 	ret = clk_prepare_enable(dsi->grf_clk);  in dw_mipi_dsi_encoder_enable()
766 		DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);  in dw_mipi_dsi_encoder_enable()
770 	dw_mipi_dsi_rockchip_config(dsi, mux);  in dw_mipi_dsi_encoder_enable()
771 	if (dsi->slave)  in dw_mipi_dsi_encoder_enable()
772 		dw_mipi_dsi_rockchip_config(dsi->slave, mux);  in dw_mipi_dsi_encoder_enable()
774 	clk_disable_unprepare(dsi->grf_clk);  in dw_mipi_dsi_encoder_enable()
779 	struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);  in dw_mipi_dsi_encoder_disable()  local
781 	if (dsi->slave)  in dw_mipi_dsi_encoder_disable()
782 		pm_runtime_put(dsi->slave->dev);  in dw_mipi_dsi_encoder_disable()
783 	pm_runtime_put(dsi->dev);  in dw_mipi_dsi_encoder_disable()
793 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,  in rockchip_dsi_drm_create_encoder()  argument
796 	struct drm_encoder *encoder = &dsi->encoder;  in rockchip_dsi_drm_create_encoder()
800 							     dsi->dev->of_node);  in rockchip_dsi_drm_create_encoder()
814 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)  in dw_mipi_dsi_rockchip_find_second()  argument
819 	match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);  in dw_mipi_dsi_rockchip_find_second()
821 	local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);  in dw_mipi_dsi_rockchip_find_second()
830 		if (node == dsi->dev->of_node)  in dw_mipi_dsi_rockchip_find_second()
877 	struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);  in dw_mipi_dsi_rockchip_bind()  local
883 	second = dw_mipi_dsi_rockchip_find_second(dsi);  in dw_mipi_dsi_rockchip_bind()
888 		master1 = of_property_read_bool(dsi->dev->of_node,  in dw_mipi_dsi_rockchip_bind()
894 			DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");  in dw_mipi_dsi_rockchip_bind()
899 			DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");  in dw_mipi_dsi_rockchip_bind()
903 		/* we are the slave in dual-DSI */  in dw_mipi_dsi_rockchip_bind()
905 			dsi->is_slave = true;  in dw_mipi_dsi_rockchip_bind()
909 		dsi->slave = dev_get_drvdata(second);  in dw_mipi_dsi_rockchip_bind()
910 		if (!dsi->slave) {  in dw_mipi_dsi_rockchip_bind()
915 		dsi->slave->is_slave = true;  in dw_mipi_dsi_rockchip_bind()
916 		dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);  in dw_mipi_dsi_rockchip_bind()
920 	ret = clk_prepare_enable(dsi->pllref_clk);  in dw_mipi_dsi_rockchip_bind()
926 	ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);  in dw_mipi_dsi_rockchip_bind()
932 	ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);  in dw_mipi_dsi_rockchip_bind()
945 	struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);  in dw_mipi_dsi_rockchip_unbind()  local
947 	if (dsi->is_slave)  in dw_mipi_dsi_rockchip_unbind()
950 	dw_mipi_dsi_unbind(dsi->dmd);  in dw_mipi_dsi_rockchip_unbind()
952 	clk_disable_unprepare(dsi->pllref_clk);  in dw_mipi_dsi_rockchip_unbind()
963 	struct dw_mipi_dsi_rockchip *dsi = priv_data;  in dw_mipi_dsi_rockchip_host_attach()  local
967 	ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);  in dw_mipi_dsi_rockchip_host_attach()
969 		DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",  in dw_mipi_dsi_rockchip_host_attach()
974 	second = dw_mipi_dsi_rockchip_find_second(dsi);  in dw_mipi_dsi_rockchip_host_attach()
993 	struct dw_mipi_dsi_rockchip *dsi = priv_data;  in dw_mipi_dsi_rockchip_host_detach()  local
996 	second = dw_mipi_dsi_rockchip_find_second(dsi);  in dw_mipi_dsi_rockchip_host_detach()
1000 	component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);  in dw_mipi_dsi_rockchip_host_detach()
1014 	struct dw_mipi_dsi_rockchip *dsi;  in dw_mipi_dsi_rockchip_probe()  local
1020 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);  in dw_mipi_dsi_rockchip_probe()
1021 	if (!dsi)  in dw_mipi_dsi_rockchip_probe()
1025 	dsi->base = devm_ioremap_resource(dev, res);  in dw_mipi_dsi_rockchip_probe()
1026 	if (IS_ERR(dsi->base)) {  in dw_mipi_dsi_rockchip_probe()
1027 		DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");  in dw_mipi_dsi_rockchip_probe()
1028 		return PTR_ERR(dsi->base);  in dw_mipi_dsi_rockchip_probe()
1034 			dsi->cdata = &cdata[i];  in dw_mipi_dsi_rockchip_probe()
1041 	if (!dsi->cdata) {  in dw_mipi_dsi_rockchip_probe()
1042 		DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);  in dw_mipi_dsi_rockchip_probe()
1047 	dsi->phy = devm_phy_optional_get(dev, "dphy");  in dw_mipi_dsi_rockchip_probe()
1048 	if (IS_ERR(dsi->phy)) {  in dw_mipi_dsi_rockchip_probe()
1049 		ret = PTR_ERR(dsi->phy);  in dw_mipi_dsi_rockchip_probe()
1054 	dsi->pllref_clk = devm_clk_get(dev, "ref");  in dw_mipi_dsi_rockchip_probe()
1055 	if (IS_ERR(dsi->pllref_clk)) {  in dw_mipi_dsi_rockchip_probe()
1056 		if (dsi->phy) {  in dw_mipi_dsi_rockchip_probe()
1061 			dsi->pllref_clk = NULL;  in dw_mipi_dsi_rockchip_probe()
1063 			ret = PTR_ERR(dsi->pllref_clk);  in dw_mipi_dsi_rockchip_probe()
1071 	if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {  in dw_mipi_dsi_rockchip_probe()
1072 		dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");  in dw_mipi_dsi_rockchip_probe()
1073 		if (IS_ERR(dsi->phy_cfg_clk)) {  in dw_mipi_dsi_rockchip_probe()
1074 			ret = PTR_ERR(dsi->phy_cfg_clk);  in dw_mipi_dsi_rockchip_probe()
1081 	if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {  in dw_mipi_dsi_rockchip_probe()
1082 		dsi->grf_clk = devm_clk_get(dev, "grf");  in dw_mipi_dsi_rockchip_probe()
1083 		if (IS_ERR(dsi->grf_clk)) {  in dw_mipi_dsi_rockchip_probe()
1084 			ret = PTR_ERR(dsi->grf_clk);  in dw_mipi_dsi_rockchip_probe()
1090 	dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");  in dw_mipi_dsi_rockchip_probe()
1091 	if (IS_ERR(dsi->grf_regmap)) {  in dw_mipi_dsi_rockchip_probe()
1092 		DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");  in dw_mipi_dsi_rockchip_probe()
1093 		return PTR_ERR(dsi->grf_regmap);  in dw_mipi_dsi_rockchip_probe()
1096 	dsi->dev = dev;  in dw_mipi_dsi_rockchip_probe()
1097 	dsi->pdata.base = dsi->base;  in dw_mipi_dsi_rockchip_probe()
1098 	dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;  in dw_mipi_dsi_rockchip_probe()
1099 	dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;  in dw_mipi_dsi_rockchip_probe()
1100 	dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;  in dw_mipi_dsi_rockchip_probe()
1101 	dsi->pdata.priv_data = dsi;  in dw_mipi_dsi_rockchip_probe()
1102 	platform_set_drvdata(pdev, dsi);  in dw_mipi_dsi_rockchip_probe()
1104 	dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);  in dw_mipi_dsi_rockchip_probe()
1105 	if (IS_ERR(dsi->dmd)) {  in dw_mipi_dsi_rockchip_probe()
1106 		ret = PTR_ERR(dsi->dmd);  in dw_mipi_dsi_rockchip_probe()
1116 	clk_disable_unprepare(dsi->pllref_clk);  in dw_mipi_dsi_rockchip_probe()
1122 	struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);  in dw_mipi_dsi_rockchip_remove()  local
1124 	if (dsi->devcnt == 0)  in dw_mipi_dsi_rockchip_remove()
1125 		component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);  in dw_mipi_dsi_rockchip_remove()
1127 	dw_mipi_dsi_remove(dsi->dmd);  in dw_mipi_dsi_rockchip_remove()
1218 	 .compatible = "rockchip,px30-mipi-dsi",
1221 	 .compatible = "rockchip,rk3288-mipi-dsi",
1224 	 .compatible = "rockchip,rk3399-mipi-dsi",
1236 		.name	= "dw-mipi-dsi-rockchip",