Lines Matching +full:r8a7795 +full:- +full:lvds
1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
37 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_read()
39 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); in rcar_du_crtc_read()
44 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_write()
46 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); in rcar_du_crtc_write()
51 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_clr()
53 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_clr()
54 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr()
59 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_set()
61 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_set()
62 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set); in rcar_du_crtc_set()
67 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_dsysr_clr_set()
69 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set; in rcar_du_crtc_dsysr_clr_set()
70 rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr); in rcar_du_crtc_dsysr_clr_set()
73 /* -----------------------------------------------------------------------------
89 unsigned long best_diff = (unsigned long)-1; in rcar_du_dpll_divider()
97 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out in rcar_du_dpll_divider()
98 * +-> | | | in rcar_du_dpll_divider()
100 * +---------------- [1/N] <------------+ in rcar_du_dpll_divider()
102 * fclkout = fvco / P / FDPLL -- (1) in rcar_du_dpll_divider()
106 * fvco = fin * P * N / M -- (2) in rcar_du_dpll_divider()
124 for (n = 119; n > 38; n--) { in rcar_du_dpll_divider()
126 * This code only runs on 64-bit architectures, the in rcar_du_dpll_divider()
127 * unsigned long type can thus be used for 64-bit in rcar_du_dpll_divider()
129 * warning on 32-bit architectures. in rcar_du_dpll_divider()
146 diff = abs((long)output - (long)target); in rcar_du_dpll_divider()
149 dpll->n = n; in rcar_du_dpll_divider()
150 dpll->m = m; in rcar_du_dpll_divider()
151 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
152 dpll->output = output; in rcar_du_dpll_divider()
162 dev_dbg(rcrtc->dev->dev, in rcar_du_dpll_divider()
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
185 if (params->diff == 0) in rcar_du_escr_divider()
193 div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1; in rcar_du_escr_divider()
194 diff = abs(rate / (div + 1) - target); in rcar_du_escr_divider()
200 if (diff < params->diff) { in rcar_du_escr_divider()
201 params->clk = clk; in rcar_du_escr_divider()
202 params->rate = rate; in rcar_du_escr_divider()
203 params->diff = diff; in rcar_du_escr_divider()
204 params->escr = escr | div; in rcar_du_escr_divider()
209 { .soc_id = "r8a7795", .revision = "ES1.*" },
215 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; in rcar_du_crtc_set_display_timing()
216 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_set_display_timing()
217 unsigned long mode_clock = mode->clock * 1000; in rcar_du_crtc_set_display_timing()
221 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) { in rcar_du_crtc_set_display_timing()
236 * desired frequency, coupled with a /2 post-divider. Restrict in rcar_du_crtc_set_display_timing()
238 * no post-divider when a display PLL is present (as shown by in rcar_du_crtc_set_display_timing()
239 * the workaround breaking HDMI output on M3-W during testing). in rcar_du_crtc_set_display_timing()
246 extclk = clk_get_rate(rcrtc->extclock); in rcar_du_crtc_set_display_timing()
254 if (rcrtc->index == 1) in rcar_du_crtc_set_display_timing()
261 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); in rcar_du_crtc_set_display_timing()
264 } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) { in rcar_du_crtc_set_display_timing()
266 * Use the LVDS PLL output as the dot clock when outputting to in rcar_du_crtc_set_display_timing()
267 * the LVDS encoder on an SoC that supports this clock routing in rcar_du_crtc_set_display_timing()
273 struct du_clk_params params = { .diff = (unsigned long)-1 }; in rcar_du_crtc_set_display_timing()
275 rcar_du_escr_divider(rcrtc->clock, mode_clock, in rcar_du_crtc_set_display_timing()
277 if (rcrtc->extclock) in rcar_du_crtc_set_display_timing()
278 rcar_du_escr_divider(rcrtc->extclock, mode_clock, in rcar_du_crtc_set_display_timing()
281 dev_dbg(rcrtc->dev->dev, "mode clock %lu %s rate %lu\n", in rcar_du_crtc_set_display_timing()
282 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext", in rcar_du_crtc_set_display_timing()
289 dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); in rcar_du_crtc_set_display_timing()
291 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); in rcar_du_crtc_set_display_timing()
292 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); in rcar_du_crtc_set_display_timing()
295 dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0) in rcar_du_crtc_set_display_timing()
296 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0) in rcar_du_crtc_set_display_timing()
297 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0) in rcar_du_crtc_set_display_timing()
302 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19); in rcar_du_crtc_set_display_timing()
303 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + in rcar_du_crtc_set_display_timing()
304 mode->hdisplay - 19); in rcar_du_crtc_set_display_timing()
305 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end - in rcar_du_crtc_set_display_timing()
306 mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
307 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); in rcar_du_crtc_set_display_timing()
309 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
310 mode->crtc_vsync_end - 2); in rcar_du_crtc_set_display_timing()
311 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
312 mode->crtc_vsync_end + in rcar_du_crtc_set_display_timing()
313 mode->crtc_vdisplay - 2); in rcar_du_crtc_set_display_timing()
314 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
315 mode->crtc_vsync_end + in rcar_du_crtc_set_display_timing()
316 mode->crtc_vsync_start - 1); in rcar_du_crtc_set_display_timing()
317 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); in rcar_du_crtc_set_display_timing()
319 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
320 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); in rcar_du_crtc_set_display_timing()
325 return plane->plane.state->normalized_zpos; in plane_zpos()
331 return to_rcar_plane_state(plane->plane.state)->format; in plane_format()
337 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_update_planes()
345 for (i = 0; i < rcrtc->group->num_planes; ++i) { in rcar_du_crtc_update_planes()
346 struct rcar_du_plane *plane = &rcrtc->group->planes[i]; in rcar_du_crtc_update_planes()
349 if (plane->plane.state->crtc != &rcrtc->crtc || in rcar_du_crtc_update_planes()
350 !plane->plane.state->visible) in rcar_du_crtc_update_planes()
354 for (j = num_planes++; j > 0; --j) { in rcar_du_crtc_update_planes()
355 if (plane_zpos(planes[j-1]) <= plane_zpos(plane)) in rcar_du_crtc_update_planes()
357 planes[j] = planes[j-1]; in rcar_du_crtc_update_planes()
361 prio += plane_format(plane)->planes * 4; in rcar_du_crtc_update_planes()
366 struct drm_plane_state *state = plane->plane.state; in rcar_du_crtc_update_planes()
367 unsigned int index = to_rcar_plane_state(state)->hwindex; in rcar_du_crtc_update_planes()
369 prio -= 4; in rcar_du_crtc_update_planes()
373 if (plane_format(plane)->planes == 2) { in rcar_du_crtc_update_planes()
376 prio -= 4; in rcar_du_crtc_update_planes()
384 if (rcdu->info->gen < 3) { in rcar_du_crtc_update_planes()
385 dspr = (rcrtc->index % 2) + 1; in rcar_du_crtc_update_planes()
386 hwplanes = 1 << (rcrtc->index % 2); in rcar_du_crtc_update_planes()
388 dspr = (rcrtc->index % 2) ? 3 : 1; in rcar_du_crtc_update_planes()
389 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0); in rcar_du_crtc_update_planes()
402 mutex_lock(&rcrtc->group->lock); in rcar_du_crtc_update_planes()
404 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes in rcar_du_crtc_update_planes()
405 : rcrtc->group->dptsr_planes & ~hwplanes; in rcar_du_crtc_update_planes()
407 if (dptsr_planes != rcrtc->group->dptsr_planes) { in rcar_du_crtc_update_planes()
408 rcar_du_group_write(rcrtc->group, DPTSR, in rcar_du_crtc_update_planes()
410 rcrtc->group->dptsr_planes = dptsr_planes; in rcar_du_crtc_update_planes()
412 if (rcrtc->group->used_crtcs) in rcar_du_crtc_update_planes()
413 rcar_du_group_restart(rcrtc->group); in rcar_du_crtc_update_planes()
417 if (rcrtc->group->need_restart) in rcar_du_crtc_update_planes()
418 rcar_du_group_restart(rcrtc->group); in rcar_du_crtc_update_planes()
420 mutex_unlock(&rcrtc->group->lock); in rcar_du_crtc_update_planes()
422 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, in rcar_du_crtc_update_planes()
426 /* -----------------------------------------------------------------------------
433 struct drm_device *dev = rcrtc->crtc.dev; in rcar_du_crtc_finish_page_flip()
436 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
437 event = rcrtc->event; in rcar_du_crtc_finish_page_flip()
438 rcrtc->event = NULL; in rcar_du_crtc_finish_page_flip()
439 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
444 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
445 drm_crtc_send_vblank_event(&rcrtc->crtc, event); in rcar_du_crtc_finish_page_flip()
446 wake_up(&rcrtc->flip_wait); in rcar_du_crtc_finish_page_flip()
447 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
449 drm_crtc_vblank_put(&rcrtc->crtc); in rcar_du_crtc_finish_page_flip()
454 struct drm_device *dev = rcrtc->crtc.dev; in rcar_du_crtc_page_flip_pending()
458 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_page_flip_pending()
459 pending = rcrtc->event != NULL; in rcar_du_crtc_page_flip_pending()
460 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_page_flip_pending()
467 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_wait_page_flip()
469 if (wait_event_timeout(rcrtc->flip_wait, in rcar_du_crtc_wait_page_flip()
474 dev_warn(rcdu->dev, "page flip timeout\n"); in rcar_du_crtc_wait_page_flip()
479 /* -----------------------------------------------------------------------------
486 struct drm_property_blob *drm_lut = state->gamma_lut; in rcar_du_cmm_check()
488 struct device *dev = rcrtc->dev->dev; in rcar_du_cmm_check()
496 drm_lut->length); in rcar_du_cmm_check()
497 return -EINVAL; in rcar_du_cmm_check()
505 struct drm_property_blob *drm_lut = crtc->state->gamma_lut; in rcar_du_cmm_setup()
509 if (!rcrtc->cmm) in rcar_du_cmm_setup()
513 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data; in rcar_du_cmm_setup()
515 rcar_cmm_setup(rcrtc->cmm, &cmm_config); in rcar_du_cmm_setup()
518 /* -----------------------------------------------------------------------------
530 rcar_du_group_set_routing(rcrtc->group); in rcar_du_crtc_setup()
533 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); in rcar_du_crtc_setup()
536 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_setup()
540 drm_crtc_vblank_on(&rcrtc->crtc); in rcar_du_crtc_setup()
548 * Guard against double-get, as the function is called from both the in rcar_du_crtc_get()
551 if (rcrtc->initialized) in rcar_du_crtc_get()
554 ret = clk_prepare_enable(rcrtc->clock); in rcar_du_crtc_get()
558 ret = clk_prepare_enable(rcrtc->extclock); in rcar_du_crtc_get()
562 ret = rcar_du_group_get(rcrtc->group); in rcar_du_crtc_get()
567 rcrtc->initialized = true; in rcar_du_crtc_get()
572 clk_disable_unprepare(rcrtc->extclock); in rcar_du_crtc_get()
574 clk_disable_unprepare(rcrtc->clock); in rcar_du_crtc_get()
580 rcar_du_group_put(rcrtc->group); in rcar_du_crtc_put()
582 clk_disable_unprepare(rcrtc->extclock); in rcar_du_crtc_put()
583 clk_disable_unprepare(rcrtc->clock); in rcar_du_crtc_put()
585 rcrtc->initialized = false; in rcar_du_crtc_put()
597 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE; in rcar_du_crtc_start()
602 rcar_du_group_start_stop(rcrtc->group, true); in rcar_du_crtc_start()
607 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_disable_planes()
608 struct drm_crtc *crtc = &rcrtc->crtc; in rcar_du_crtc_disable_planes()
621 spin_lock_irq(&rcrtc->vblank_lock); in rcar_du_crtc_disable_planes()
622 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); in rcar_du_crtc_disable_planes()
624 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1; in rcar_du_crtc_disable_planes()
625 spin_unlock_irq(&rcrtc->vblank_lock); in rcar_du_crtc_disable_planes()
627 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0, in rcar_du_crtc_disable_planes()
629 dev_warn(rcdu->dev, "vertical blanking timeout\n"); in rcar_du_crtc_disable_planes()
636 struct drm_crtc *crtc = &rcrtc->crtc; in rcar_du_crtc_stop()
660 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_stop()
663 if (rcrtc->cmm) in rcar_du_crtc_stop()
664 rcar_cmm_disable(rcrtc->cmm); in rcar_du_crtc_stop()
673 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_TVM_SYNC)) in rcar_du_crtc_stop()
677 rcar_du_group_start_stop(rcrtc->group, false); in rcar_du_crtc_stop()
680 /* -----------------------------------------------------------------------------
696 rstate->outputs = 0; in rcar_du_crtc_atomic_check()
698 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) { in rcar_du_crtc_atomic_check()
702 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) in rcar_du_crtc_atomic_check()
706 rstate->outputs |= BIT(renc->output); in rcar_du_crtc_atomic_check()
716 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state); in rcar_du_crtc_atomic_enable()
717 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_atomic_enable()
719 if (rcrtc->cmm) in rcar_du_crtc_atomic_enable()
720 rcar_cmm_enable(rcrtc->cmm); in rcar_du_crtc_atomic_enable()
724 * On D3/E3 the dot clock is provided by the LVDS encoder attached to in rcar_du_crtc_atomic_enable()
726 * the LVDS output is disabled. in rcar_du_crtc_atomic_enable()
728 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) && in rcar_du_crtc_atomic_enable()
729 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) { in rcar_du_crtc_atomic_enable()
731 rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index]; in rcar_du_crtc_atomic_enable()
733 &crtc->state->adjusted_mode; in rcar_du_crtc_atomic_enable()
736 bridge = drm_bridge_chain_get_first_bridge(&encoder->base); in rcar_du_crtc_atomic_enable()
737 rcar_lvds_clk_enable(bridge, mode->clock * 1000); in rcar_du_crtc_atomic_enable()
755 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_atomic_disable()
760 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) && in rcar_du_crtc_atomic_disable()
761 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) { in rcar_du_crtc_atomic_disable()
763 rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index]; in rcar_du_crtc_atomic_disable()
767 * Disable the LVDS clock output, see in rcar_du_crtc_atomic_disable()
770 bridge = drm_bridge_chain_get_first_bridge(&encoder->base); in rcar_du_crtc_atomic_disable()
774 spin_lock_irq(&crtc->dev->event_lock); in rcar_du_crtc_atomic_disable()
775 if (crtc->state->event) { in rcar_du_crtc_atomic_disable()
776 drm_crtc_send_vblank_event(crtc, crtc->state->event); in rcar_du_crtc_atomic_disable()
777 crtc->state->event = NULL; in rcar_du_crtc_atomic_disable()
779 spin_unlock_irq(&crtc->dev->event_lock); in rcar_du_crtc_atomic_disable()
787 WARN_ON(!crtc->state->enable); in rcar_du_crtc_atomic_begin()
794 * operation in .atomic_enable() will in that case be a no-op, and the in rcar_du_crtc_atomic_begin()
798 * following get call will be a no-op. There is thus no need to balance in rcar_du_crtc_atomic_begin()
804 if (crtc->state->color_mgmt_changed && !crtc->state->active_changed) in rcar_du_crtc_atomic_begin()
807 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_atomic_begin()
815 struct drm_device *dev = rcrtc->crtc.dev; in rcar_du_crtc_atomic_flush()
820 if (crtc->state->event) { in rcar_du_crtc_atomic_flush()
823 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_atomic_flush()
824 rcrtc->event = crtc->state->event; in rcar_du_crtc_atomic_flush()
825 crtc->state->event = NULL; in rcar_du_crtc_atomic_flush()
826 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_atomic_flush()
829 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_atomic_flush()
838 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_mode_valid()
839 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; in rcar_du_crtc_mode_valid()
849 if (mode->htotal - mode->hsync_start < 20) in rcar_du_crtc_mode_valid()
852 vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1); in rcar_du_crtc_mode_valid()
870 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_crc_init()
873 int i = -1; in rcar_du_crtc_crc_init()
876 if (rcdu->info->gen < 3) in rcar_du_crtc_crc_init()
880 count = rcrtc->vsp->num_planes + 1; in rcar_du_crtc_crc_init()
890 for (i = 0; i < rcrtc->vsp->num_planes; ++i) { in rcar_du_crtc_crc_init()
891 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane; in rcar_du_crtc_crc_init()
894 sprintf(name, "plane%u", plane->base.id); in rcar_du_crtc_crc_init()
900 rcrtc->sources = sources; in rcar_du_crtc_crc_init()
901 rcrtc->sources_count = count; in rcar_du_crtc_crc_init()
907 i--; in rcar_du_crtc_crc_init()
916 if (!rcrtc->sources) in rcar_du_crtc_crc_cleanup()
919 for (i = 0; i < rcrtc->sources_count; i++) in rcar_du_crtc_crc_cleanup()
920 kfree(rcrtc->sources[i]); in rcar_du_crtc_crc_cleanup()
921 kfree(rcrtc->sources); in rcar_du_crtc_crc_cleanup()
923 rcrtc->sources = NULL; in rcar_du_crtc_crc_cleanup()
924 rcrtc->sources_count = 0; in rcar_du_crtc_crc_cleanup()
933 if (WARN_ON(!crtc->state)) in rcar_du_crtc_atomic_duplicate_state()
936 state = to_rcar_crtc_state(crtc->state); in rcar_du_crtc_atomic_duplicate_state()
941 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state); in rcar_du_crtc_atomic_duplicate_state()
943 return ©->state; in rcar_du_crtc_atomic_duplicate_state()
966 if (crtc->state) { in rcar_du_crtc_reset()
967 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state); in rcar_du_crtc_reset()
968 crtc->state = NULL; in rcar_du_crtc_reset()
975 state->crc.source = VSP1_DU_CRC_NONE; in rcar_du_crtc_reset()
976 state->crc.index = 0; in rcar_du_crtc_reset()
978 __drm_atomic_helper_crtc_reset(crtc, &state->state); in rcar_du_crtc_reset()
987 rcrtc->vblank_enable = true; in rcar_du_crtc_enable_vblank()
997 rcrtc->vblank_enable = false; in rcar_du_crtc_disable_vblank()
1028 for (i = 0; i < rcrtc->vsp->num_planes; ++i) { in rcar_du_crtc_parse_crc_source()
1029 if (index == rcrtc->vsp->planes[i].plane.base.id) in rcar_du_crtc_parse_crc_source()
1034 return -EINVAL; in rcar_du_crtc_parse_crc_source()
1046 return -EINVAL; in rcar_du_crtc_verify_crc_source()
1058 *count = rcrtc->sources_count; in rcar_du_crtc_get_crc_sources()
1059 return rcrtc->sources; in rcar_du_crtc_get_crc_sources()
1082 state = drm_atomic_state_alloc(crtc->dev); in rcar_du_crtc_set_crc_source()
1084 ret = -ENOMEM; in rcar_du_crtc_set_crc_source()
1088 state->acquire_ctx = &ctx; in rcar_du_crtc_set_crc_source()
1096 rcrtc_state->crc.source = source; in rcar_du_crtc_set_crc_source()
1097 rcrtc_state->crc.index = index; in rcar_du_crtc_set_crc_source()
1104 if (ret == -EDEADLK) { in rcar_du_crtc_set_crc_source()
1145 /* -----------------------------------------------------------------------------
1152 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_irq()
1156 spin_lock(&rcrtc->vblank_lock); in rcar_du_crtc_irq()
1167 if (rcrtc->vblank_count) { in rcar_du_crtc_irq()
1168 if (--rcrtc->vblank_count == 0) in rcar_du_crtc_irq()
1169 wake_up(&rcrtc->vblank_wait); in rcar_du_crtc_irq()
1173 spin_unlock(&rcrtc->vblank_lock); in rcar_du_crtc_irq()
1176 if (rcdu->info->gen < 3) { in rcar_du_crtc_irq()
1177 drm_crtc_handle_vblank(&rcrtc->crtc); in rcar_du_crtc_irq()
1187 /* -----------------------------------------------------------------------------
1198 struct rcar_du_device *rcdu = rgrp->dev; in rcar_du_crtc_create()
1199 struct platform_device *pdev = to_platform_device(rcdu->dev); in rcar_du_crtc_create()
1200 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex]; in rcar_du_crtc_create()
1201 struct drm_crtc *crtc = &rcrtc->crtc; in rcar_du_crtc_create()
1218 rcrtc->clock = devm_clk_get(rcdu->dev, name); in rcar_du_crtc_create()
1219 if (IS_ERR(rcrtc->clock)) { in rcar_du_crtc_create()
1220 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex); in rcar_du_crtc_create()
1221 return PTR_ERR(rcrtc->clock); in rcar_du_crtc_create()
1225 clk = devm_clk_get(rcdu->dev, clk_name); in rcar_du_crtc_create()
1227 rcrtc->extclock = clk; in rcar_du_crtc_create()
1228 } else if (PTR_ERR(clk) == -EPROBE_DEFER) { in rcar_du_crtc_create()
1229 return -EPROBE_DEFER; in rcar_du_crtc_create()
1230 } else if (rcdu->info->dpll_mask & BIT(hwindex)) { in rcar_du_crtc_create()
1236 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret); in rcar_du_crtc_create()
1240 init_waitqueue_head(&rcrtc->flip_wait); in rcar_du_crtc_create()
1241 init_waitqueue_head(&rcrtc->vblank_wait); in rcar_du_crtc_create()
1242 spin_lock_init(&rcrtc->vblank_lock); in rcar_du_crtc_create()
1244 rcrtc->dev = rcdu; in rcar_du_crtc_create()
1245 rcrtc->group = rgrp; in rcar_du_crtc_create()
1246 rcrtc->mmio_offset = mmio_offsets[hwindex]; in rcar_du_crtc_create()
1247 rcrtc->index = hwindex; in rcar_du_crtc_create()
1248 rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC; in rcar_du_crtc_create()
1251 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane; in rcar_du_crtc_create()
1253 primary = &rgrp->planes[swindex % 2].plane; in rcar_du_crtc_create()
1255 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL, in rcar_du_crtc_create()
1256 rcdu->info->gen <= 2 ? in rcar_du_crtc_create()
1263 if (rcdu->cmms[swindex]) { in rcar_du_crtc_create()
1264 rcrtc->cmm = rcdu->cmms[swindex]; in rcar_du_crtc_create()
1265 rgrp->cmms_mask |= BIT(hwindex % 2); in rcar_du_crtc_create()
1284 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex); in rcar_du_crtc_create()
1288 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags, in rcar_du_crtc_create()
1289 dev_name(rcdu->dev), rcrtc); in rcar_du_crtc_create()
1291 dev_err(rcdu->dev, in rcar_du_crtc_create()