Lines Matching +full:battery +full:- +full:profile
350 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps()
357 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
392 if (pi->override_dynamic_mgpg && (hw_rev == 0)) in trinity_gfx_powergating_initialize()
549 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
551 if (pi->enable_mg_clock_gating) in trinity_enable_clock_power_gating()
553 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
555 if (pi->enable_mg_clock_gating) { in trinity_enable_clock_power_gating()
559 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
561 if (pi->enable_gfx_dynamic_mgpg) in trinity_enable_clock_power_gating()
563 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
571 if (pi->enable_gfx_power_gating) in trinity_disable_clock_power_gating()
573 if (pi->enable_gfx_dynamic_mgpg) in trinity_disable_clock_power_gating()
575 if (pi->enable_gfx_clock_gating) in trinity_disable_clock_power_gating()
577 if (pi->enable_mg_clock_gating) { in trinity_disable_clock_power_gating()
639 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid); in trinity_set_vid()
722 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
723 trinity_set_vid(rdev, index, pl->vddc_index); in trinity_program_power_level()
724 trinity_set_ss_dividers(rdev, index, pl->ss_divider_index); in trinity_program_power_level()
725 trinity_set_ds_dividers(rdev, index, pl->ds_divider_index); in trinity_program_power_level()
726 trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); in trinity_program_power_level()
727 trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state); in trinity_program_power_level()
728 trinity_set_display_wm(rdev, index, pl->display_wm); in trinity_program_power_level()
729 trinity_set_vce_wm(rdev, index, pl->vce_wm); in trinity_program_power_level()
730 trinity_set_at(rdev, index, pi->at[index]); in trinity_program_power_level()
772 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_dpm_enabled()
777 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_dpm_enabled()
782 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_dpm_enabled()
817 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_level_0()
846 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
848 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
849 trinity_program_power_level(rdev, &new_ps->levels[i], i); in trinity_program_power_levels_0_to_n()
853 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
862 trinity_program_power_level(rdev, &pi->boot_pl, 0); in trinity_program_bootup_state()
873 u32 uvdstates = (ps->vclk_low_divider | in trinity_setup_uvd_clock_table()
874 ps->vclk_high_divider << 8 | in trinity_setup_uvd_clock_table()
875 ps->dclk_low_divider << 16 | in trinity_setup_uvd_clock_table()
876 ps->dclk_high_divider << 24); in trinity_setup_uvd_clock_table()
891 val = (p + tp - 1) / tp; in trinity_setup_uvd_dpm_interval()
898 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
910 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
911 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
912 (ps1->vclk_low_divider == ps2->vclk_low_divider) && in trinity_uvd_clocks_equal()
913 (ps1->vclk_high_divider == ps2->vclk_high_divider) && in trinity_uvd_clocks_equal()
914 (ps1->dclk_low_divider == ps2->dclk_low_divider) && in trinity_uvd_clocks_equal()
915 (ps1->dclk_high_divider == ps2->dclk_high_divider)) in trinity_uvd_clocks_equal()
927 if (pi->enable_gfx_power_gating) { in trinity_setup_uvd_clocks()
931 if (pi->uvd_dpm) { in trinity_setup_uvd_clocks()
943 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
954 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
957 if (pi->enable_gfx_power_gating) { in trinity_setup_uvd_clocks()
969 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
970 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
983 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
984 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
994 if ((old_rps->evclk != new_rps->evclk) || in trinity_set_vce_clock()
995 (old_rps->ecclk != new_rps->ecclk)) { in trinity_set_vce_clock()
997 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
1001 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1011 value |= HT((pi->thermal_auto_throttling + 49) * 8); in trinity_program_ttt()
1012 value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8); in trinity_program_ttt()
1035 ni = (p + tp - 1) / tp; in trinity_program_sclk_dpm()
1054 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in trinity_set_thermal_temperature_range()
1055 return -EINVAL; in trinity_set_thermal_temperature_range()
1061 rdev->pm.dpm.thermal.min_temp = low_temp; in trinity_set_thermal_temperature_range()
1062 rdev->pm.dpm.thermal.max_temp = high_temp; in trinity_set_thermal_temperature_range()
1073 pi->current_rps = *rps; in trinity_update_current_ps()
1074 pi->current_ps = *new_ps; in trinity_update_current_ps()
1075 pi->current_rps.ps_priv = &pi->current_ps; in trinity_update_current_ps()
1084 pi->requested_rps = *rps; in trinity_update_requested_ps()
1085 pi->requested_ps = *new_ps; in trinity_update_requested_ps()
1086 pi->requested_rps.ps_priv = &pi->requested_ps; in trinity_update_requested_ps()
1093 if (pi->enable_bapm) { in trinity_dpm_enable_bapm()
1108 return -EINVAL; in trinity_dpm_enable()
1114 if (pi->enable_auto_thermal_throttling) { in trinity_dpm_enable()
1124 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_enable()
1136 if (rdev->irq.installed && in trinity_dpm_late_enable()
1137 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in trinity_dpm_late_enable()
1143 rdev->irq.dpm_thermal = true; in trinity_dpm_late_enable()
1166 if (rdev->irq.installed && in trinity_dpm_disable()
1167 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in trinity_dpm_disable()
1168 rdev->irq.dpm_thermal = false; in trinity_dpm_disable()
1172 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_disable()
1179 pi->min_sclk_did = in trinity_get_min_sclk_divider()
1190 if (pi->sys_info.nb_dpm_enable) { in trinity_setup_nbp_sim()
1193 nbpsconfig |= (Dpm0PgNbPsLo(new_ps->Dpm0PgNbPsLo) | in trinity_setup_nbp_sim()
1194 Dpm0PgNbPsHi(new_ps->Dpm0PgNbPsHi) | in trinity_setup_nbp_sim()
1195 DpmXNbPsLo(new_ps->DpmXNbPsLo) | in trinity_setup_nbp_sim()
1196 DpmXNbPsHi(new_ps->DpmXNbPsHi)); in trinity_setup_nbp_sim()
1205 struct radeon_ps *rps = &pi->current_rps; in trinity_dpm_force_performance_level()
1209 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1214 return -EINVAL; in trinity_dpm_force_performance_level()
1216 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1220 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
1227 rdev->pm.dpm.forced_level = level; in trinity_dpm_force_performance_level()
1235 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in trinity_dpm_pre_set_power_state()
1241 &pi->requested_rps, in trinity_dpm_pre_set_power_state()
1242 &pi->current_rps); in trinity_dpm_pre_set_power_state()
1250 struct radeon_ps *new_ps = &pi->requested_rps; in trinity_dpm_set_power_state()
1251 struct radeon_ps *old_ps = &pi->current_rps; in trinity_dpm_set_power_state()
1254 if (pi->enable_dpm) { in trinity_dpm_set_power_state()
1255 if (pi->enable_bapm) in trinity_dpm_set_power_state()
1256 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power); in trinity_dpm_set_power_state()
1276 struct radeon_ps *new_ps = &pi->requested_rps; in trinity_dpm_post_set_power_state()
1296 if (pi->enable_dpm) {
1312 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit); in trinity_convert_voltage_index_to_value()
1320 return (155000 - delta) / 100; in trinity_convert_voltage_index_to_value()
1328 ps->num_levels = 1; in trinity_patch_boot_state()
1329 ps->nbps_flags = 0; in trinity_patch_boot_state()
1330 ps->bapm_flags = 0; in trinity_patch_boot_state()
1331 ps->levels[0] = pi->boot_pl; in trinity_patch_boot_state()
1345 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in trinity_construct_boot_state()
1346 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in trinity_construct_boot_state()
1347 pi->boot_pl.ds_divider_index = 0; in trinity_construct_boot_state()
1348 pi->boot_pl.ss_divider_index = 0; in trinity_construct_boot_state()
1349 pi->boot_pl.allow_gnb_slow = 1; in trinity_construct_boot_state()
1350 pi->boot_pl.force_nbp_state = 0; in trinity_construct_boot_state()
1351 pi->boot_pl.display_wm = 0; in trinity_construct_boot_state()
1352 pi->boot_pl.vce_wm = 0; in trinity_construct_boot_state()
1353 pi->current_ps.num_levels = 1; in trinity_construct_boot_state()
1354 pi->current_ps.levels[0] = pi->boot_pl; in trinity_construct_boot_state()
1369 if (!pi->enable_sclk_ds) in trinity_get_sleep_divider_id_from_clock()
1372 for (i = TRINITY_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { in trinity_get_sleep_divider_id_from_clock()
1387 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { in trinity_get_valid_engine_clock()
1388 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) in trinity_get_valid_engine_clock()
1389 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; in trinity_get_valid_engine_clock()
1392 if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries) in trinity_get_valid_engine_clock()
1403 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in trinity_patch_thermal_state()
1409 current_vddc = current_ps->levels[current_index].vddc_index; in trinity_patch_thermal_state()
1410 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()
1412 current_vddc = pi->boot_pl.vddc_index; in trinity_patch_thermal_state()
1413 current_sclk = pi->boot_pl.sclk; in trinity_patch_thermal_state()
1416 ps->levels[0].vddc_index = current_vddc; in trinity_patch_thermal_state()
1418 if (ps->levels[0].sclk > current_sclk) in trinity_patch_thermal_state()
1419 ps->levels[0].sclk = current_sclk; in trinity_patch_thermal_state()
1421 ps->levels[0].ds_divider_index = in trinity_patch_thermal_state()
1422 trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); in trinity_patch_thermal_state()
1423 ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index; in trinity_patch_thermal_state()
1424 ps->levels[0].allow_gnb_slow = 1; in trinity_patch_thermal_state()
1425 ps->levels[0].force_nbp_state = 0; in trinity_patch_thermal_state()
1426 ps->levels[0].display_wm = 0; in trinity_patch_thermal_state()
1427 ps->levels[0].vce_wm = in trinity_patch_thermal_state()
1428 trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); in trinity_patch_thermal_state()
1434 if (ps == NULL || ps->num_levels <= 1) in trinity_calculate_display_wm()
1436 else if (ps->num_levels == 2) { in trinity_calculate_display_wm()
1444 else if (ps->levels[index].sclk < 30000) in trinity_calculate_display_wm()
1458 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1459 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1478 if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) { in trinity_adjust_uvd_state()
1493 ps->vclk_low_divider = in trinity_adjust_uvd_state()
1494 pi->sys_info.uvd_clock_table_entries[high_index].vclk_did; in trinity_adjust_uvd_state()
1495 ps->dclk_low_divider = in trinity_adjust_uvd_state()
1496 pi->sys_info.uvd_clock_table_entries[high_index].dclk_did; in trinity_adjust_uvd_state()
1497 ps->vclk_high_divider = in trinity_adjust_uvd_state()
1498 pi->sys_info.uvd_clock_table_entries[low_index].vclk_did; in trinity_adjust_uvd_state()
1499 ps->dclk_high_divider = in trinity_adjust_uvd_state()
1500 pi->sys_info.uvd_clock_table_entries[low_index].dclk_did; in trinity_adjust_uvd_state()
1508 int ret = -EINVAL; in trinity_get_vce_clock_voltage()
1510 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in trinity_get_vce_clock_voltage()
1513 (table && (table->count == 0))) { in trinity_get_vce_clock_voltage()
1518 for (i = 0; i < table->count; i++) { in trinity_get_vce_clock_voltage()
1519 if ((evclk <= table->entries[i].evclk) && in trinity_get_vce_clock_voltage()
1520 (ecclk <= table->entries[i].ecclk)) { in trinity_get_vce_clock_voltage()
1521 *voltage = table->entries[i].v; in trinity_get_vce_clock_voltage()
1529 *voltage = table->entries[table->count - 1].v; in trinity_get_vce_clock_voltage()
1542 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ in trinity_apply_state_adjust_rules()
1543 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in trinity_apply_state_adjust_rules()
1547 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_apply_state_adjust_rules()
1549 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) in trinity_apply_state_adjust_rules()
1554 if (new_rps->vce_active) { in trinity_apply_state_adjust_rules()
1555 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in trinity_apply_state_adjust_rules()
1556 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in trinity_apply_state_adjust_rules()
1558 new_rps->evclk = 0; in trinity_apply_state_adjust_rules()
1559 new_rps->ecclk = 0; in trinity_apply_state_adjust_rules()
1562 for (i = 0; i < ps->num_levels; i++) { in trinity_apply_state_adjust_rules()
1563 if (ps->levels[i].vddc_index < min_voltage) in trinity_apply_state_adjust_rules()
1564 ps->levels[i].vddc_index = min_voltage; in trinity_apply_state_adjust_rules()
1566 if (ps->levels[i].sclk < min_sclk) in trinity_apply_state_adjust_rules()
1567 ps->levels[i].sclk = in trinity_apply_state_adjust_rules()
1571 if (new_rps->vce_active) { in trinity_apply_state_adjust_rules()
1573 if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in trinity_apply_state_adjust_rules()
1574 ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in trinity_apply_state_adjust_rules()
1576 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
1577 if (ps->levels[i].vddc_index < min_vce_voltage) in trinity_apply_state_adjust_rules()
1578 ps->levels[i].vddc_index = min_vce_voltage; in trinity_apply_state_adjust_rules()
1581 ps->levels[i].ds_divider_index = in trinity_apply_state_adjust_rules()
1582 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); in trinity_apply_state_adjust_rules()
1584 ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index; in trinity_apply_state_adjust_rules()
1586 ps->levels[i].allow_gnb_slow = 1; in trinity_apply_state_adjust_rules()
1587 ps->levels[i].force_nbp_state = 0; in trinity_apply_state_adjust_rules()
1588 ps->levels[i].display_wm = in trinity_apply_state_adjust_rules()
1590 ps->levels[i].vce_wm = in trinity_apply_state_adjust_rules()
1591 trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); in trinity_apply_state_adjust_rules()
1594 if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) || in trinity_apply_state_adjust_rules()
1595 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) in trinity_apply_state_adjust_rules()
1596 ps->bapm_flags |= TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE; in trinity_apply_state_adjust_rules()
1598 if (pi->sys_info.nb_dpm_enable) { in trinity_apply_state_adjust_rules()
1599 ps->Dpm0PgNbPsLo = 0x1; in trinity_apply_state_adjust_rules()
1600 ps->Dpm0PgNbPsHi = 0x0; in trinity_apply_state_adjust_rules()
1601 ps->DpmXNbPsLo = 0x2; in trinity_apply_state_adjust_rules()
1602 ps->DpmXNbPsHi = 0x1; in trinity_apply_state_adjust_rules()
1604 if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) || in trinity_apply_state_adjust_rules()
1605 … ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) { in trinity_apply_state_adjust_rules()
1606 force_high = ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) || in trinity_apply_state_adjust_rules()
1607 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) && in trinity_apply_state_adjust_rules()
1608 (pi->sys_info.uma_channel_number == 1))); in trinity_apply_state_adjust_rules()
1610 ps->Dpm0PgNbPsLo = force_high ? 0x2 : 0x3; in trinity_apply_state_adjust_rules()
1611 ps->Dpm0PgNbPsHi = 0x1; in trinity_apply_state_adjust_rules()
1612 ps->DpmXNbPsLo = force_high ? 0x2 : 0x3; in trinity_apply_state_adjust_rules()
1613 ps->DpmXNbPsHi = 0x2; in trinity_apply_state_adjust_rules()
1614 ps->levels[ps->num_levels - 1].allow_gnb_slow = 0; in trinity_apply_state_adjust_rules()
1629 if (pi->voltage_drop_in_dce)
1637 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_add_dccac_value()
1638 u64 disp_clk = rdev->clock.default_dispclk / 100; in trinity_add_dccac_value()
1645 (32 - gpu_cac_avrg_cntl_window_size)); in trinity_add_dccac_value()
1654 if (pi->voltage_drop_in_dce) in trinity_dpm_display_configuration_changed()
1687 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in trinity_parse_pplib_non_clock_info()
1688 rps->class = le16_to_cpu(non_clock_info->usClassification); in trinity_parse_pplib_non_clock_info()
1689 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in trinity_parse_pplib_non_clock_info()
1692 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1693 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1695 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1696 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1699 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in trinity_parse_pplib_non_clock_info()
1700 rdev->pm.dpm.boot_ps = rps; in trinity_parse_pplib_non_clock_info()
1703 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in trinity_parse_pplib_non_clock_info()
1704 rdev->pm.dpm.uvd_ps = rps; in trinity_parse_pplib_non_clock_info()
1713 struct trinity_pl *pl = &ps->levels[index]; in trinity_parse_pplib_clock_info()
1716 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); in trinity_parse_pplib_clock_info()
1717 sclk |= clock_info->sumo.ucEngineClockHigh << 16; in trinity_parse_pplib_clock_info()
1718 pl->sclk = sclk; in trinity_parse_pplib_clock_info()
1719 pl->vddc_index = clock_info->sumo.vddcIndex; in trinity_parse_pplib_clock_info()
1721 ps->num_levels = index + 1; in trinity_parse_pplib_clock_info()
1723 if (pi->enable_sclk_ds) { in trinity_parse_pplib_clock_info()
1724 pl->ds_divider_index = 5; in trinity_parse_pplib_clock_info()
1725 pl->ss_divider_index = 5; in trinity_parse_pplib_clock_info()
1731 struct radeon_mode_info *mode_info = &rdev->mode_info; in trinity_parse_power_table()
1746 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in trinity_parse_power_table()
1748 return -EINVAL; in trinity_parse_power_table()
1749 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in trinity_parse_power_table()
1752 (mode_info->atom_context->bios + data_offset + in trinity_parse_power_table()
1753 le16_to_cpu(power_info->pplib.usStateArrayOffset)); in trinity_parse_power_table()
1755 (mode_info->atom_context->bios + data_offset + in trinity_parse_power_table()
1756 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); in trinity_parse_power_table()
1758 (mode_info->atom_context->bios + data_offset + in trinity_parse_power_table()
1759 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); in trinity_parse_power_table()
1761 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in trinity_parse_power_table()
1764 if (!rdev->pm.dpm.ps) in trinity_parse_power_table()
1765 return -ENOMEM; in trinity_parse_power_table()
1766 power_state_offset = (u8 *)state_array->states; in trinity_parse_power_table()
1767 for (i = 0; i < state_array->ucNumEntries; i++) { in trinity_parse_power_table()
1770 non_clock_array_index = power_state->v2.nonClockInfoIndex; in trinity_parse_power_table()
1772 &non_clock_info_array->nonClockInfo[non_clock_array_index]; in trinity_parse_power_table()
1773 if (!rdev->pm.power_state[i].clock_info) in trinity_parse_power_table()
1774 return -EINVAL; in trinity_parse_power_table()
1777 kfree(rdev->pm.dpm.ps); in trinity_parse_power_table()
1778 return -ENOMEM; in trinity_parse_power_table()
1780 rdev->pm.dpm.ps[i].ps_priv = ps; in trinity_parse_power_table()
1782 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in trinity_parse_power_table()
1783 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in trinity_parse_power_table()
1785 if (clock_array_index >= clock_info_array->ucNumEntries) in trinity_parse_power_table()
1790 ((u8 *)&clock_info_array->clockInfo[0] + in trinity_parse_power_table()
1791 (clock_array_index * clock_info_array->ucEntrySize)); in trinity_parse_power_table()
1793 &rdev->pm.dpm.ps[i], k, in trinity_parse_power_table()
1797 trinity_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in trinity_parse_power_table()
1799 non_clock_info_array->ucEntrySize); in trinity_parse_power_table()
1800 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in trinity_parse_power_table()
1802 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in trinity_parse_power_table()
1807 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in trinity_parse_power_table()
1809 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; in trinity_parse_power_table()
1810 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); in trinity_parse_power_table()
1811 sclk |= clock_info->sumo.ucEngineClockHigh << 16; in trinity_parse_power_table()
1812 rdev->pm.dpm.vce_states[i].sclk = sclk; in trinity_parse_power_table()
1813 rdev->pm.dpm.vce_states[i].mclk = 0; in trinity_parse_power_table()
1835 divider = (did - 64) * 50 + 1600; in trinity_convert_did_to_freq()
1837 divider = (did - 96) * 100 + 3200; in trinity_convert_did_to_freq()
1843 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider; in trinity_convert_did_to_freq()
1849 struct radeon_mode_info *mode_info = &rdev->mode_info; in trinity_parse_sys_info_table()
1856 if (atom_parse_data_header(mode_info->atom_context, index, NULL, in trinity_parse_sys_info_table()
1858 igp_info = (union igp_info *)(mode_info->atom_context->bios + in trinity_parse_sys_info_table()
1863 return -EINVAL; in trinity_parse_sys_info_table()
1865 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock); in trinity_parse_sys_info_table()
1866 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock); in trinity_parse_sys_info_table()
1867 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock); in trinity_parse_sys_info_table()
1868 pi->sys_info.dentist_vco_freq = le32_to_cpu(igp_info->info_7.ulDentistVCOFreq); in trinity_parse_sys_info_table()
1869 pi->sys_info.bootup_nb_voltage_index = in trinity_parse_sys_info_table()
1870 le16_to_cpu(igp_info->info_7.usBootUpNBVoltage); in trinity_parse_sys_info_table()
1871 if (igp_info->info_7.ucHtcTmpLmt == 0) in trinity_parse_sys_info_table()
1872 pi->sys_info.htc_tmp_lmt = 203; in trinity_parse_sys_info_table()
1874 pi->sys_info.htc_tmp_lmt = igp_info->info_7.ucHtcTmpLmt; in trinity_parse_sys_info_table()
1875 if (igp_info->info_7.ucHtcHystLmt == 0) in trinity_parse_sys_info_table()
1876 pi->sys_info.htc_hyst_lmt = 5; in trinity_parse_sys_info_table()
1878 pi->sys_info.htc_hyst_lmt = igp_info->info_7.ucHtcHystLmt; in trinity_parse_sys_info_table()
1879 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in trinity_parse_sys_info_table()
1883 if (pi->enable_nbps_policy) in trinity_parse_sys_info_table()
1884 pi->sys_info.nb_dpm_enable = igp_info->info_7.ucNBDPMEnable; in trinity_parse_sys_info_table()
1886 pi->sys_info.nb_dpm_enable = 0; in trinity_parse_sys_info_table()
1889 pi->sys_info.nbp_mclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateMemclkFreq[i]); in trinity_parse_sys_info_table()
1890 pi->sys_info.nbp_nclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateNClkFreq[i]); in trinity_parse_sys_info_table()
1893 pi->sys_info.nbp_voltage_index[0] = le16_to_cpu(igp_info->info_7.usNBP0Voltage); in trinity_parse_sys_info_table()
1894 pi->sys_info.nbp_voltage_index[1] = le16_to_cpu(igp_info->info_7.usNBP1Voltage); in trinity_parse_sys_info_table()
1895 pi->sys_info.nbp_voltage_index[2] = le16_to_cpu(igp_info->info_7.usNBP2Voltage); in trinity_parse_sys_info_table()
1896 pi->sys_info.nbp_voltage_index[3] = le16_to_cpu(igp_info->info_7.usNBP3Voltage); in trinity_parse_sys_info_table()
1898 if (!pi->sys_info.nb_dpm_enable) { in trinity_parse_sys_info_table()
1900 pi->sys_info.nbp_mclk[i] = pi->sys_info.nbp_mclk[0]; in trinity_parse_sys_info_table()
1901 pi->sys_info.nbp_nclk[i] = pi->sys_info.nbp_nclk[0]; in trinity_parse_sys_info_table()
1902 pi->sys_info.nbp_voltage_index[i] = pi->sys_info.nbp_voltage_index[0]; in trinity_parse_sys_info_table()
1906 pi->sys_info.uma_channel_number = igp_info->info_7.ucUMAChannelNumber; in trinity_parse_sys_info_table()
1909 &pi->sys_info.sclk_voltage_mapping_table, in trinity_parse_sys_info_table()
1910 igp_info->info_7.sAvail_SCLK); in trinity_parse_sys_info_table()
1911 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, in trinity_parse_sys_info_table()
1912 igp_info->info_7.sAvail_SCLK); in trinity_parse_sys_info_table()
1914 pi->sys_info.uvd_clock_table_entries[0].vclk_did = in trinity_parse_sys_info_table()
1915 igp_info->info_7.ucDPMState0VclkFid; in trinity_parse_sys_info_table()
1916 pi->sys_info.uvd_clock_table_entries[1].vclk_did = in trinity_parse_sys_info_table()
1917 igp_info->info_7.ucDPMState1VclkFid; in trinity_parse_sys_info_table()
1918 pi->sys_info.uvd_clock_table_entries[2].vclk_did = in trinity_parse_sys_info_table()
1919 igp_info->info_7.ucDPMState2VclkFid; in trinity_parse_sys_info_table()
1920 pi->sys_info.uvd_clock_table_entries[3].vclk_did = in trinity_parse_sys_info_table()
1921 igp_info->info_7.ucDPMState3VclkFid; in trinity_parse_sys_info_table()
1923 pi->sys_info.uvd_clock_table_entries[0].dclk_did = in trinity_parse_sys_info_table()
1924 igp_info->info_7.ucDPMState0DclkFid; in trinity_parse_sys_info_table()
1925 pi->sys_info.uvd_clock_table_entries[1].dclk_did = in trinity_parse_sys_info_table()
1926 igp_info->info_7.ucDPMState1DclkFid; in trinity_parse_sys_info_table()
1927 pi->sys_info.uvd_clock_table_entries[2].dclk_did = in trinity_parse_sys_info_table()
1928 igp_info->info_7.ucDPMState2DclkFid; in trinity_parse_sys_info_table()
1929 pi->sys_info.uvd_clock_table_entries[3].dclk_did = in trinity_parse_sys_info_table()
1930 igp_info->info_7.ucDPMState3DclkFid; in trinity_parse_sys_info_table()
1933 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1935 pi->sys_info.uvd_clock_table_entries[i].vclk_did); in trinity_parse_sys_info_table()
1936 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1938 pi->sys_info.uvd_clock_table_entries[i].dclk_did); in trinity_parse_sys_info_table()
1954 return -ENOMEM; in trinity_dpm_init()
1955 rdev->pm.dpm.priv = pi; in trinity_dpm_init()
1958 pi->at[i] = TRINITY_AT_DFLT; in trinity_dpm_init()
1960 if (radeon_bapm == -1) { in trinity_dpm_init()
1962 * bapm enabled when switching between AC and battery in trinity_dpm_init()
1967 if (rdev->pdev->subsystem_vendor == 0x1462) in trinity_dpm_init()
1968 pi->enable_bapm = true; in trinity_dpm_init()
1970 pi->enable_bapm = false; in trinity_dpm_init()
1972 pi->enable_bapm = false; in trinity_dpm_init()
1974 pi->enable_bapm = true; in trinity_dpm_init()
1976 pi->enable_nbps_policy = true; in trinity_dpm_init()
1977 pi->enable_sclk_ds = true; in trinity_dpm_init()
1978 pi->enable_gfx_power_gating = true; in trinity_dpm_init()
1979 pi->enable_gfx_clock_gating = true; in trinity_dpm_init()
1980 pi->enable_mg_clock_gating = false; in trinity_dpm_init()
1981 pi->enable_gfx_dynamic_mgpg = false; in trinity_dpm_init()
1982 pi->override_dynamic_mgpg = false; in trinity_dpm_init()
1983 pi->enable_auto_thermal_throttling = true; in trinity_dpm_init()
1984 pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */ in trinity_dpm_init()
1985 pi->uvd_dpm = true; /* ??? */ in trinity_dpm_init()
2005 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; in trinity_dpm_init()
2006 pi->enable_dpm = true; in trinity_dpm_init()
2017 r600_dpm_print_class_info(rps->class, rps->class2); in trinity_dpm_print_power_state()
2018 r600_dpm_print_cap_info(rps->caps); in trinity_dpm_print_power_state()
2019 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2020 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_print_power_state()
2021 struct trinity_pl *pl = &ps->levels[i]; in trinity_dpm_print_power_state()
2023 i, pl->sclk, in trinity_dpm_print_power_state()
2024 trinity_convert_voltage_index_to_value(rdev, pl->vddc_index)); in trinity_dpm_print_power_state()
2033 struct radeon_ps *rps = &pi->current_rps; in trinity_dpm_debugfs_print_current_performance_level()
2040 if (current_index >= ps->num_levels) { in trinity_dpm_debugfs_print_current_performance_level()
2041 seq_printf(m, "invalid dpm profile %d\n", current_index); in trinity_dpm_debugfs_print_current_performance_level()
2043 pl = &ps->levels[current_index]; in trinity_dpm_debugfs_print_current_performance_level()
2044 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
2046 current_index, pl->sclk, in trinity_dpm_debugfs_print_current_performance_level()
2047 trinity_convert_voltage_index_to_value(rdev, pl->vddc_index)); in trinity_dpm_debugfs_print_current_performance_level()
2054 struct radeon_ps *rps = &pi->current_rps; in trinity_dpm_get_current_sclk()
2061 if (current_index >= ps->num_levels) { in trinity_dpm_get_current_sclk()
2064 pl = &ps->levels[current_index]; in trinity_dpm_get_current_sclk()
2065 return pl->sclk; in trinity_dpm_get_current_sclk()
2073 return pi->sys_info.bootup_uma_clk; in trinity_dpm_get_current_mclk()
2082 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in trinity_dpm_fini()
2083 kfree(rdev->pm.dpm.ps[i].ps_priv); in trinity_dpm_fini()
2085 kfree(rdev->pm.dpm.ps); in trinity_dpm_fini()
2086 kfree(rdev->pm.dpm.priv); in trinity_dpm_fini()
2093 struct trinity_ps *requested_state = trinity_get_ps(&pi->requested_rps); in trinity_dpm_get_sclk()
2096 return requested_state->levels[0].sclk; in trinity_dpm_get_sclk()
2098 return requested_state->levels[requested_state->num_levels - 1].sclk; in trinity_dpm_get_sclk()
2105 return pi->sys_info.bootup_uma_clk; in trinity_dpm_get_mclk()