Lines Matching +full:0 +full:x7
51 #define DPM_NO_LIMIT 0
56 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
57 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0
63 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
64 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
66 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
68 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
70 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
72 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
74 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
76 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
78 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
80 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
82 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
101 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
103 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01
104 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
105 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
106 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08
107 #define SMU7_UVD_DPM_CONFIG_MASK 0x10
108 #define SMU7_VCE_DPM_CONFIG_MASK 0x20
109 #define SMU7_ACP_DPM_CONFIG_MASK 0x40
110 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80
111 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
113 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
114 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
115 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
116 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
117 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
118 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
149 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000