Lines Matching refs:CG_VCEPLL_FUNC_CNTL
7483 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7488 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7493 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) in si_vce_send_vcepll_ctlreq()
7499 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7520 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, in si_set_vce_clocks()
7525 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, in si_set_vce_clocks()
7540 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, in si_set_vce_clocks()
7544 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, in si_set_vce_clocks()
7546 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); in si_set_vce_clocks()
7549 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7558 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7567 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); in si_set_vce_clocks()
7578 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7583 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); in si_set_vce_clocks()