45 	struct rv6xx_power_info *pi = rdev->pm.dpm.priv;  in rv6xx_get_pi()
921 							  rdev->pm.dpm.voltage_response_time,  in rv6xx_program_voltage_timing_parameters()
925 					   rdev->pm.dpm.backbias_response_time,  in rv6xx_program_voltage_timing_parameters()
1185 	if (rdev->pm.dpm.new_active_crtcs & 1) {  in rv6xx_program_display_gap()
1188 	} else if (rdev->pm.dpm.new_active_crtcs & 2) {  in rv6xx_program_display_gap()
1298 		msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);  in rv6xx_step_sw_voltage()
1548 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in rv6xx_dpm_enable()
1553 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)  in rv6xx_dpm_enable()
1615 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in rv6xx_dpm_disable()
1633 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)  in rv6xx_dpm_disable()
1659 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in rv6xx_dpm_set_power_state()
1660 	struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;  in rv6xx_dpm_set_power_state()
1683 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in rv6xx_dpm_set_power_state()
1687 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)  in rv6xx_dpm_set_power_state()
1696 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)  in rv6xx_dpm_set_power_state()
1700 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in rv6xx_dpm_set_power_state()
1702 		msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);  in rv6xx_dpm_set_power_state()
1720 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {  in rv6xx_dpm_set_power_state()
1728 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)  in rv6xx_dpm_set_power_state()
1759 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)  in rv6xx_setup_asic()
1761 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)  in rv6xx_setup_asic()
1763 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)  in rv6xx_setup_asic()
1811 		rdev->pm.dpm.boot_ps = rps;  in rv6xx_parse_pplib_non_clock_info()
1813 		rdev->pm.dpm.uvd_ps = rps;  in rv6xx_parse_pplib_non_clock_info()
1890 	rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,  in rv6xx_parse_power_table()
1893 	if (!rdev->pm.dpm.ps)  in rv6xx_parse_power_table()
1910 				kfree(rdev->pm.dpm.ps);  in rv6xx_parse_power_table()
1913 			rdev->pm.dpm.ps[i].ps_priv = ps;  in rv6xx_parse_power_table()
1914 			rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in rv6xx_parse_power_table()
1923 							     &rdev->pm.dpm.ps[i], j,  in rv6xx_parse_power_table()
1928 	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;  in rv6xx_parse_power_table()
1942 	rdev->pm.dpm.priv = pi;  in rv6xx_dpm_init()
1952 	if (rdev->pm.dpm.voltage_response_time == 0)  in rv6xx_dpm_init()
1953 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in rv6xx_dpm_init()
1954 	if (rdev->pm.dpm.backbias_response_time == 0)  in rv6xx_dpm_init()
1955 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in rv6xx_dpm_init()
2031 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in rv6xx_dpm_debugfs_print_current_performance_level()
2056 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in rv6xx_dpm_get_current_sclk()
2079 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in rv6xx_dpm_get_current_mclk()
2103 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in rv6xx_dpm_fini()
2104 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in rv6xx_dpm_fini()
2106 	kfree(rdev->pm.dpm.ps);  in rv6xx_dpm_fini()
2107 	kfree(rdev->pm.dpm.priv);  in rv6xx_dpm_fini()
2112 	struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);  in rv6xx_dpm_get_sclk()
2122 	struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);  in rv6xx_dpm_get_mclk()
2156 	rdev->pm.dpm.forced_level = level;  in rv6xx_dpm_force_performance_level()