Lines Matching +full:ati +full:- +full:target
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
55 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut()
56 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut()
60 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
69 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
71 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
76 r = crtc->gamma_store; in avivo_crtc_load_lut()
77 g = r + crtc->gamma_size; in avivo_crtc_load_lut()
78 b = g + crtc->gamma_size; in avivo_crtc_load_lut()
87 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); in avivo_crtc_load_lut()
93 struct drm_device *dev = crtc->dev; in dce4_crtc_load_lut()
94 struct radeon_device *rdev = dev->dev_private; in dce4_crtc_load_lut()
98 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in dce4_crtc_load_lut()
99 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
102 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
103 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
106 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
107 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
109 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
110 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce4_crtc_load_lut()
112 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
113 r = crtc->gamma_store; in dce4_crtc_load_lut()
114 g = r + crtc->gamma_size; in dce4_crtc_load_lut()
115 b = g + crtc->gamma_size; in dce4_crtc_load_lut()
117 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce4_crtc_load_lut()
127 struct drm_device *dev = crtc->dev; in dce5_crtc_load_lut()
128 struct radeon_device *rdev = dev->dev_private; in dce5_crtc_load_lut()
132 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in dce5_crtc_load_lut()
136 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
139 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
141 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
143 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
147 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
150 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
151 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
154 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
155 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
157 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
158 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce5_crtc_load_lut()
160 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
161 r = crtc->gamma_store; in dce5_crtc_load_lut()
162 g = r + crtc->gamma_size; in dce5_crtc_load_lut()
163 b = g + crtc->gamma_size; in dce5_crtc_load_lut()
165 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
171 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
176 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
179 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
182 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
183 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | in dce5_crtc_load_lut()
186 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
191 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
199 struct drm_device *dev = crtc->dev; in legacy_crtc_load_lut()
200 struct radeon_device *rdev = dev->dev_private; in legacy_crtc_load_lut()
206 if (radeon_crtc->crtc_id == 0) in legacy_crtc_load_lut()
213 r = crtc->gamma_store; in legacy_crtc_load_lut()
214 g = r + crtc->gamma_size; in legacy_crtc_load_lut()
215 b = g + crtc->gamma_size; in legacy_crtc_load_lut()
226 struct drm_device *dev = crtc->dev; in radeon_crtc_load_lut()
227 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_load_lut()
229 if (!crtc->enabled) in radeon_crtc_load_lut()
256 destroy_workqueue(radeon_crtc->flip_queue); in radeon_crtc_destroy()
261 * radeon_unpin_work_func - unpin old buffer object
263 * @__work - kernel work item
274 r = radeon_bo_reserve(work->old_rbo, false); in radeon_unpin_work_func()
276 r = radeon_bo_unpin(work->old_rbo); in radeon_unpin_work_func()
280 radeon_bo_unreserve(work->old_rbo); in radeon_unpin_work_func()
284 drm_gem_object_put(&work->old_rbo->tbo.base); in radeon_unpin_work_func()
290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank()
301 * irqs are a reliable and race-free method of handling pageflip in radeon_crtc_handle_vblank()
311 spin_lock_irqsave(&rdev->ddev->event_lock, flags); in radeon_crtc_handle_vblank()
312 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { in radeon_crtc_handle_vblank()
313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " in radeon_crtc_handle_vblank()
315 radeon_crtc->flip_status, in radeon_crtc_handle_vblank()
317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); in radeon_crtc_handle_vblank()
330 * vblank. On pre-AVIVO hardware, flips also complete inside the real in radeon_crtc_handle_vblank()
335 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, in radeon_crtc_handle_vblank()
338 * This applies at least to pre-AVIVO hardware, where flips are always in radeon_crtc_handle_vblank()
343 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, in radeon_crtc_handle_vblank()
346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank()
348 /* crtc didn't flip in this target vblank interval, in radeon_crtc_handle_vblank()
356 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); in radeon_crtc_handle_vblank()
362 * radeon_crtc_handle_flip - page flip completed
371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip()
379 spin_lock_irqsave(&rdev->ddev->event_lock, flags); in radeon_crtc_handle_flip()
380 work = radeon_crtc->flip_work; in radeon_crtc_handle_flip()
381 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { in radeon_crtc_handle_flip()
382 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " in radeon_crtc_handle_flip()
384 radeon_crtc->flip_status, in radeon_crtc_handle_flip()
386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); in radeon_crtc_handle_flip()
391 radeon_crtc->flip_status = RADEON_FLIP_NONE; in radeon_crtc_handle_flip()
392 radeon_crtc->flip_work = NULL; in radeon_crtc_handle_flip()
395 if (work->event) in radeon_crtc_handle_flip()
396 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); in radeon_crtc_handle_flip()
398 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); in radeon_crtc_handle_flip()
400 drm_crtc_vblank_put(&radeon_crtc->base); in radeon_crtc_handle_flip()
401 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); in radeon_crtc_handle_flip()
402 queue_work(radeon_crtc->flip_queue, &work->unpin_work); in radeon_crtc_handle_flip()
406 * radeon_flip_work_func - page flip framebuffer
408 * @work - kernel work item
416 struct radeon_device *rdev = work->rdev; in radeon_flip_work_func()
417 struct drm_device *dev = rdev->ddev; in radeon_flip_work_func()
418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func()
420 struct drm_crtc *crtc = &radeon_crtc->base; in radeon_flip_work_func()
425 down_read(&rdev->exclusive_lock); in radeon_flip_work_func()
426 if (work->fence) { in radeon_flip_work_func()
429 fence = to_radeon_fence(work->fence); in radeon_flip_work_func()
430 if (fence && fence->rdev == rdev) { in radeon_flip_work_func()
432 if (r == -EDEADLK) { in radeon_flip_work_func()
433 up_read(&rdev->exclusive_lock); in radeon_flip_work_func()
436 } while (r == -EAGAIN); in radeon_flip_work_func()
437 down_read(&rdev->exclusive_lock); in radeon_flip_work_func()
440 r = dma_fence_wait(work->fence, false); in radeon_flip_work_func()
450 dma_fence_put(work->fence); in radeon_flip_work_func()
451 work->fence = NULL; in radeon_flip_work_func()
459 while (radeon_crtc->enabled && in radeon_flip_work_func()
460 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, in radeon_flip_work_func()
462 &crtc->hwmode) in radeon_flip_work_func()
466 ((int) (work->target_vblank - in radeon_flip_work_func()
467 crtc->funcs->get_vblank_counter(crtc)) > 0))) in radeon_flip_work_func()
471 spin_lock_irqsave(&crtc->dev->event_lock, flags); in radeon_flip_work_func()
474 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); in radeon_flip_work_func()
477 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); in radeon_flip_work_func()
479 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; in radeon_flip_work_func()
480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in radeon_flip_work_func()
481 up_read(&rdev->exclusive_lock); in radeon_flip_work_func()
488 uint32_t target, in radeon_crtc_page_flip_target() argument
491 struct drm_device *dev = crtc->dev; in radeon_crtc_page_flip_target()
492 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_page_flip_target()
504 return -ENOMEM; in radeon_crtc_page_flip_target()
506 INIT_WORK(&work->flip_work, radeon_flip_work_func); in radeon_crtc_page_flip_target()
507 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); in radeon_crtc_page_flip_target()
509 work->rdev = rdev; in radeon_crtc_page_flip_target()
510 work->crtc_id = radeon_crtc->crtc_id; in radeon_crtc_page_flip_target()
511 work->event = event; in radeon_crtc_page_flip_target()
512 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; in radeon_crtc_page_flip_target()
515 obj = crtc->primary->fb->obj[0]; in radeon_crtc_page_flip_target()
519 work->old_rbo = gem_to_radeon_bo(obj); in radeon_crtc_page_flip_target()
521 obj = fb->obj[0]; in radeon_crtc_page_flip_target()
525 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", in radeon_crtc_page_flip_target()
526 work->old_rbo, new_rbo); in radeon_crtc_page_flip_target()
538 r = -EINVAL; in radeon_crtc_page_flip_target()
542 work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv)); in radeon_crtc_page_flip_target()
548 base -= radeon_crtc->legacy_display_base_addr; in radeon_crtc_page_flip_target()
549 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; in radeon_crtc_page_flip_target()
555 int byteshift = fb->format->cpp[0] * 8 >> 4; in radeon_crtc_page_flip_target()
556 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; in radeon_crtc_page_flip_target()
557 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); in radeon_crtc_page_flip_target()
560 int offset = crtc->y * pitch_pixels + crtc->x; in radeon_crtc_page_flip_target()
561 switch (fb->format->cpp[0] * 8) { in radeon_crtc_page_flip_target()
581 work->base = base; in radeon_crtc_page_flip_target()
582 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + in radeon_crtc_page_flip_target()
583 crtc->funcs->get_vblank_counter(crtc); in radeon_crtc_page_flip_target()
586 spin_lock_irqsave(&crtc->dev->event_lock, flags); in radeon_crtc_page_flip_target()
588 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { in radeon_crtc_page_flip_target()
590 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in radeon_crtc_page_flip_target()
591 r = -EBUSY; in radeon_crtc_page_flip_target()
594 radeon_crtc->flip_status = RADEON_FLIP_PENDING; in radeon_crtc_page_flip_target()
595 radeon_crtc->flip_work = work; in radeon_crtc_page_flip_target()
598 crtc->primary->fb = fb; in radeon_crtc_page_flip_target()
600 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in radeon_crtc_page_flip_target()
602 queue_work(radeon_crtc->flip_queue, &work->flip_work); in radeon_crtc_page_flip_target()
616 drm_gem_object_put(&work->old_rbo->tbo.base); in radeon_crtc_page_flip_target()
617 dma_fence_put(work->fence); in radeon_crtc_page_flip_target()
632 if (!set || !set->crtc) in radeon_crtc_set_config()
633 return -EINVAL; in radeon_crtc_set_config()
635 dev = set->crtc->dev; in radeon_crtc_set_config()
637 ret = pm_runtime_get_sync(dev->dev); in radeon_crtc_set_config()
639 pm_runtime_put_autosuspend(dev->dev); in radeon_crtc_set_config()
645 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) in radeon_crtc_set_config()
646 if (crtc->enabled) in radeon_crtc_set_config()
649 pm_runtime_mark_last_busy(dev->dev); in radeon_crtc_set_config()
651 rdev = dev->dev_private; in radeon_crtc_set_config()
654 if (active && !rdev->have_disp_power_ref) { in radeon_crtc_set_config()
655 rdev->have_disp_power_ref = true; in radeon_crtc_set_config()
660 if (!active && rdev->have_disp_power_ref) { in radeon_crtc_set_config()
661 pm_runtime_put_autosuspend(dev->dev); in radeon_crtc_set_config()
662 rdev->have_disp_power_ref = false; in radeon_crtc_set_config()
666 pm_runtime_put_autosuspend(dev->dev); in radeon_crtc_set_config()
685 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_init()
692 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); in radeon_crtc_init()
694 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); in radeon_crtc_init()
695 radeon_crtc->crtc_id = index; in radeon_crtc_init()
696 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); in radeon_crtc_init()
697 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
699 if (rdev->family >= CHIP_BONAIRE) { in radeon_crtc_init()
700 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; in radeon_crtc_init()
701 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; in radeon_crtc_init()
703 radeon_crtc->max_cursor_width = CURSOR_WIDTH; in radeon_crtc_init()
704 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; in radeon_crtc_init()
706 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; in radeon_crtc_init()
707 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; in radeon_crtc_init()
710 radeon_crtc->mode_set.crtc = &radeon_crtc->base; in radeon_crtc_init()
711 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); in radeon_crtc_init()
712 radeon_crtc->mode_set.num_connectors = 0; in radeon_crtc_init()
715 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) in radeon_crtc_init()
781 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in radeon_print_display_setup()
784 DRM_INFO(" %s\n", connector->name); in radeon_print_display_setup()
785 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in radeon_print_display_setup()
786 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); in radeon_print_display_setup()
787 if (radeon_connector->ddc_bus) { in radeon_print_display_setup()
789 radeon_connector->ddc_bus->rec.mask_clk_reg, in radeon_print_display_setup()
790 radeon_connector->ddc_bus->rec.mask_data_reg, in radeon_print_display_setup()
791 radeon_connector->ddc_bus->rec.a_clk_reg, in radeon_print_display_setup()
792 radeon_connector->ddc_bus->rec.a_data_reg, in radeon_print_display_setup()
793 radeon_connector->ddc_bus->rec.en_clk_reg, in radeon_print_display_setup()
794 radeon_connector->ddc_bus->rec.en_data_reg, in radeon_print_display_setup()
795 radeon_connector->ddc_bus->rec.y_clk_reg, in radeon_print_display_setup()
796 radeon_connector->ddc_bus->rec.y_data_reg); in radeon_print_display_setup()
797 if (radeon_connector->router.ddc_valid) in radeon_print_display_setup()
799 radeon_connector->router.ddc_mux_control_pin, in radeon_print_display_setup()
800 radeon_connector->router.ddc_mux_state); in radeon_print_display_setup()
801 if (radeon_connector->router.cd_valid) in radeon_print_display_setup()
803 radeon_connector->router.cd_mux_control_pin, in radeon_print_display_setup()
804 radeon_connector->router.cd_mux_state); in radeon_print_display_setup()
806 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || in radeon_print_display_setup()
807 connector->connector_type == DRM_MODE_CONNECTOR_DVII || in radeon_print_display_setup()
808 connector->connector_type == DRM_MODE_CONNECTOR_DVID || in radeon_print_display_setup()
809 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || in radeon_print_display_setup()
810 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || in radeon_print_display_setup()
811 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) in radeon_print_display_setup()
812 …DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); in radeon_print_display_setup()
815 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in radeon_print_display_setup()
817 devices = radeon_encoder->devices & radeon_connector->devices; in radeon_print_display_setup()
820 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
822 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
824 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
826 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
828 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
830 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
832 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
834 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
836 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
838 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
840 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
849 struct radeon_device *rdev = dev->dev_private; in radeon_setup_enc_conn()
852 if (rdev->bios) { in radeon_setup_enc_conn()
853 if (rdev->is_atom_bios) { in radeon_setup_enc_conn()
877 * avivo_reduce_ratio - fractional number reduction
914 * avivo_get_fb_ref_div - feedback and ref divider calculation
946 * radeon_compute_pll_avivo - compute PLL paramaters
966 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
976 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
977 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
979 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
985 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
986 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
988 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
990 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
991 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
992 ref_div_max = pll->reference_div; in radeon_compute_pll_avivo()
993 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
995 ref_div_max = min(pll->max_ref_div, 7u); in radeon_compute_pll_avivo()
997 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo()
1000 if (pll->flags & RADEON_PLL_USE_POST_DIV) { in radeon_compute_pll_avivo()
1001 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
1002 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1006 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_avivo()
1007 vco_min = pll->lcd_pll_out_min; in radeon_compute_pll_avivo()
1008 vco_max = pll->lcd_pll_out_max; in radeon_compute_pll_avivo()
1010 vco_min = pll->pll_out_min; in radeon_compute_pll_avivo()
1011 vco_max = pll->pll_out_max; in radeon_compute_pll_avivo()
1014 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1022 if (post_div_min < pll->min_post_div) in radeon_compute_pll_avivo()
1023 post_div_min = pll->min_post_div; in radeon_compute_pll_avivo()
1027 --post_div_max; in radeon_compute_pll_avivo()
1028 if (post_div_max > pll->max_post_div) in radeon_compute_pll_avivo()
1029 post_div_max = pll->max_post_div; in radeon_compute_pll_avivo()
1034 den = pll->reference_freq; in radeon_compute_pll_avivo()
1040 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
1050 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1054 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { in radeon_compute_pll_avivo()
1071 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { in radeon_compute_pll_avivo()
1072 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); in radeon_compute_pll_avivo()
1081 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1089 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + in radeon_compute_pll_avivo()
1090 (pll->reference_freq * *frac_fb_div_p)) / in radeon_compute_pll_avivo()
1095 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", in radeon_compute_pll_avivo()
1100 /* pre-avivo */
1119 uint32_t min_ref_div = pll->min_ref_div; in radeon_compute_pll_legacy()
1120 uint32_t max_ref_div = pll->max_ref_div; in radeon_compute_pll_legacy()
1121 uint32_t min_post_div = pll->min_post_div; in radeon_compute_pll_legacy()
1122 uint32_t max_post_div = pll->max_post_div; in radeon_compute_pll_legacy()
1125 uint32_t best_vco = pll->best_vco; in radeon_compute_pll_legacy()
1130 uint32_t best_freq = -1; in radeon_compute_pll_legacy()
1136 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy()
1139 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_legacy()
1140 pll_out_min = pll->lcd_pll_out_min; in radeon_compute_pll_legacy()
1141 pll_out_max = pll->lcd_pll_out_max; in radeon_compute_pll_legacy()
1143 pll_out_min = pll->pll_out_min; in radeon_compute_pll_legacy()
1144 pll_out_max = pll->pll_out_max; in radeon_compute_pll_legacy()
1150 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_legacy()
1151 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()
1153 while (min_ref_div < max_ref_div-1) { in radeon_compute_pll_legacy()
1155 uint32_t pll_in = pll->reference_freq / mid; in radeon_compute_pll_legacy()
1156 if (pll_in < pll->pll_in_min) in radeon_compute_pll_legacy()
1158 else if (pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1165 if (pll->flags & RADEON_PLL_USE_POST_DIV) in radeon_compute_pll_legacy()
1166 min_post_div = max_post_div = pll->post_div; in radeon_compute_pll_legacy()
1168 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_legacy()
1169 min_fractional_feed_div = pll->min_frac_feedback_div; in radeon_compute_pll_legacy()
1170 max_fractional_feed_div = pll->max_frac_feedback_div; in radeon_compute_pll_legacy()
1173 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { in radeon_compute_pll_legacy()
1176 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) in radeon_compute_pll_legacy()
1180 if (pll->flags & RADEON_PLL_LEGACY) { in radeon_compute_pll_legacy()
1194 uint32_t pll_in = pll->reference_freq / ref_div; in radeon_compute_pll_legacy()
1195 uint32_t min_feed_div = pll->min_feedback_div; in radeon_compute_pll_legacy()
1196 uint32_t max_feed_div = pll->max_feedback_div + 1; in radeon_compute_pll_legacy()
1198 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1210 tmp = (uint64_t)pll->reference_freq * feedback_div; in radeon_compute_pll_legacy()
1223 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; in radeon_compute_pll_legacy()
1224 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; in radeon_compute_pll_legacy()
1227 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { in radeon_compute_pll_legacy()
1231 error = freq - current_freq; in radeon_compute_pll_legacy()
1233 error = abs(current_freq - freq); in radeon_compute_pll_legacy()
1234 vco_diff = abs(vco - best_vco); in radeon_compute_pll_legacy()
1238 ((best_error > 100 && error < best_error - 100) || in radeon_compute_pll_legacy()
1239 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { in radeon_compute_pll_legacy()
1248 if (best_freq == -1) { in radeon_compute_pll_legacy()
1256 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || in radeon_compute_pll_legacy()
1257 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || in radeon_compute_pll_legacy()
1258 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || in radeon_compute_pll_legacy()
1259 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || in radeon_compute_pll_legacy()
1260 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || in radeon_compute_pll_legacy()
1261 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { in radeon_compute_pll_legacy()
1289 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", in radeon_compute_pll_legacy()
1308 fb->obj[0] = obj; in radeon_framebuffer_init()
1312 fb->obj[0] = NULL; in radeon_framebuffer_init()
1327 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); in radeon_user_framebuffer_create()
1329 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " in radeon_user_framebuffer_create()
1330 "can't create framebuffer\n", mode_cmd->handles[0]); in radeon_user_framebuffer_create()
1331 return ERR_PTR(-ENOENT); in radeon_user_framebuffer_create()
1334 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ in radeon_user_framebuffer_create()
1335 if (obj->import_attach) { in radeon_user_framebuffer_create()
1337 return ERR_PTR(-EINVAL); in radeon_user_framebuffer_create()
1343 return ERR_PTR(-ENOMEM); in radeon_user_framebuffer_create()
1369 { TV_STD_PAL_M, "pal-m" },
1370 { TV_STD_PAL_60, "pal-60" },
1371 { TV_STD_NTSC_J, "ntsc-j" },
1372 { TV_STD_SCART_PAL, "scart-pal" },
1373 { TV_STD_PAL_CN, "pal-cn" },
1406 if (rdev->is_atom_bios) { in radeon_modeset_create_props()
1407 rdev->mode_info.coherent_mode_property = in radeon_modeset_create_props()
1408 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); in radeon_modeset_create_props()
1409 if (!rdev->mode_info.coherent_mode_property) in radeon_modeset_create_props()
1410 return -ENOMEM; in radeon_modeset_create_props()
1415 rdev->mode_info.tmds_pll_property = in radeon_modeset_create_props()
1416 drm_property_create_enum(rdev->ddev, 0, in radeon_modeset_create_props()
1421 rdev->mode_info.load_detect_property = in radeon_modeset_create_props()
1422 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); in radeon_modeset_create_props()
1423 if (!rdev->mode_info.load_detect_property) in radeon_modeset_create_props()
1424 return -ENOMEM; in radeon_modeset_create_props()
1426 drm_mode_create_scaling_mode_property(rdev->ddev); in radeon_modeset_create_props()
1429 rdev->mode_info.tv_std_property = in radeon_modeset_create_props()
1430 drm_property_create_enum(rdev->ddev, 0, in radeon_modeset_create_props()
1435 rdev->mode_info.underscan_property = in radeon_modeset_create_props()
1436 drm_property_create_enum(rdev->ddev, 0, in radeon_modeset_create_props()
1440 rdev->mode_info.underscan_hborder_property = in radeon_modeset_create_props()
1441 drm_property_create_range(rdev->ddev, 0, in radeon_modeset_create_props()
1443 if (!rdev->mode_info.underscan_hborder_property) in radeon_modeset_create_props()
1444 return -ENOMEM; in radeon_modeset_create_props()
1446 rdev->mode_info.underscan_vborder_property = in radeon_modeset_create_props()
1447 drm_property_create_range(rdev->ddev, 0, in radeon_modeset_create_props()
1449 if (!rdev->mode_info.underscan_vborder_property) in radeon_modeset_create_props()
1450 return -ENOMEM; in radeon_modeset_create_props()
1453 rdev->mode_info.audio_property = in radeon_modeset_create_props()
1454 drm_property_create_enum(rdev->ddev, 0, in radeon_modeset_create_props()
1459 rdev->mode_info.dither_property = in radeon_modeset_create_props()
1460 drm_property_create_enum(rdev->ddev, 0, in radeon_modeset_create_props()
1465 rdev->mode_info.output_csc_property = in radeon_modeset_create_props()
1466 drm_property_create_enum(rdev->ddev, 0, in radeon_modeset_create_props()
1483 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && in radeon_update_display_priority()
1484 !(rdev->flags & RADEON_IS_IGP)) in radeon_update_display_priority()
1485 rdev->disp_priority = 2; in radeon_update_display_priority()
1487 rdev->disp_priority = 0; in radeon_update_display_priority()
1489 rdev->disp_priority = radeon_disp_priority; in radeon_update_display_priority()
1501 rdev->mode_info.afmt[i] = NULL; in radeon_afmt_init()
1513 0x13830 - 0x7030, in radeon_afmt_init()
1534 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1535 if (rdev->mode_info.afmt[i]) { in radeon_afmt_init()
1536 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; in radeon_afmt_init()
1537 rdev->mode_info.afmt[i]->id = i; in radeon_afmt_init()
1542 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1543 if (rdev->mode_info.afmt[0]) { in radeon_afmt_init()
1544 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; in radeon_afmt_init()
1545 rdev->mode_info.afmt[0]->id = 0; in radeon_afmt_init()
1547 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1548 if (rdev->mode_info.afmt[1]) { in radeon_afmt_init()
1549 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; in radeon_afmt_init()
1550 rdev->mode_info.afmt[1]->id = 1; in radeon_afmt_init()
1554 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1555 if (rdev->mode_info.afmt[0]) { in radeon_afmt_init()
1556 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; in radeon_afmt_init()
1557 rdev->mode_info.afmt[0]->id = 0; in radeon_afmt_init()
1560 if (rdev->family >= CHIP_R600) { in radeon_afmt_init()
1561 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1562 if (rdev->mode_info.afmt[1]) { in radeon_afmt_init()
1563 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; in radeon_afmt_init()
1564 rdev->mode_info.afmt[1]->id = 1; in radeon_afmt_init()
1575 kfree(rdev->mode_info.afmt[i]); in radeon_afmt_fini()
1576 rdev->mode_info.afmt[i] = NULL; in radeon_afmt_fini()
1585 drm_mode_config_init(rdev->ddev); in radeon_modeset_init()
1586 rdev->mode_info.mode_config_initialized = true; in radeon_modeset_init()
1588 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; in radeon_modeset_init()
1590 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) in radeon_modeset_init()
1591 rdev->ddev->mode_config.async_page_flip = true; in radeon_modeset_init()
1594 rdev->ddev->mode_config.max_width = 16384; in radeon_modeset_init()
1595 rdev->ddev->mode_config.max_height = 16384; in radeon_modeset_init()
1597 rdev->ddev->mode_config.max_width = 8192; in radeon_modeset_init()
1598 rdev->ddev->mode_config.max_height = 8192; in radeon_modeset_init()
1600 rdev->ddev->mode_config.max_width = 4096; in radeon_modeset_init()
1601 rdev->ddev->mode_config.max_height = 4096; in radeon_modeset_init()
1604 rdev->ddev->mode_config.preferred_depth = 24; in radeon_modeset_init()
1605 rdev->ddev->mode_config.prefer_shadow = 1; in radeon_modeset_init()
1607 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; in radeon_modeset_init()
1617 /* check combios for a valid hardcoded EDID - Sun servers */ in radeon_modeset_init()
1618 if (!rdev->is_atom_bios) { in radeon_modeset_init()
1624 for (i = 0; i < rdev->num_crtc; i++) { in radeon_modeset_init()
1625 radeon_crtc_init(rdev->ddev, i); in radeon_modeset_init()
1629 ret = radeon_setup_enc_conn(rdev->ddev); in radeon_modeset_init()
1635 if (rdev->is_atom_bios) { in radeon_modeset_init()
1647 drm_kms_helper_poll_init(rdev->ddev); in radeon_modeset_init()
1657 if (rdev->mode_info.mode_config_initialized) { in radeon_modeset_fini()
1658 drm_kms_helper_poll_fini(rdev->ddev); in radeon_modeset_fini()
1660 drm_helper_force_disable_all(rdev->ddev); in radeon_modeset_fini()
1663 drm_mode_config_cleanup(rdev->ddev); in radeon_modeset_fini()
1664 rdev->mode_info.mode_config_initialized = false; in radeon_modeset_fini()
1667 kfree(rdev->mode_info.bios_hardcoded_edid); in radeon_modeset_fini()
1676 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ in is_hdtv_mode()
1677 (mode->vdisplay == 576) || /* 576p */ in is_hdtv_mode()
1678 (mode->vdisplay == 720) || /* 720p */ in is_hdtv_mode()
1679 (mode->vdisplay == 1080)) /* 1080p */ in is_hdtv_mode()
1689 struct drm_device *dev = crtc->dev; in radeon_crtc_scaling_mode_fixup()
1690 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_scaling_mode_fixup()
1699 radeon_crtc->h_border = 0; in radeon_crtc_scaling_mode_fixup()
1700 radeon_crtc->v_border = 0; in radeon_crtc_scaling_mode_fixup()
1702 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in radeon_crtc_scaling_mode_fixup()
1703 if (encoder->crtc != crtc) in radeon_crtc_scaling_mode_fixup()
1710 if (radeon_encoder->rmx_type == RMX_OFF) in radeon_crtc_scaling_mode_fixup()
1711 radeon_crtc->rmx_type = RMX_OFF; in radeon_crtc_scaling_mode_fixup()
1712 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || in radeon_crtc_scaling_mode_fixup()
1713 mode->vdisplay < radeon_encoder->native_mode.vdisplay) in radeon_crtc_scaling_mode_fixup()
1714 radeon_crtc->rmx_type = radeon_encoder->rmx_type; in radeon_crtc_scaling_mode_fixup()
1716 radeon_crtc->rmx_type = RMX_OFF; in radeon_crtc_scaling_mode_fixup()
1718 memcpy(&radeon_crtc->native_mode, in radeon_crtc_scaling_mode_fixup()
1719 &radeon_encoder->native_mode, in radeon_crtc_scaling_mode_fixup()
1721 src_v = crtc->mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1722 dst_v = radeon_crtc->native_mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1723 src_h = crtc->mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1724 dst_h = radeon_crtc->native_mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1728 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && in radeon_crtc_scaling_mode_fixup()
1729 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || in radeon_crtc_scaling_mode_fixup()
1730 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && in radeon_crtc_scaling_mode_fixup()
1733 if (radeon_encoder->underscan_hborder != 0) in radeon_crtc_scaling_mode_fixup()
1734 radeon_crtc->h_border = radeon_encoder->underscan_hborder; in radeon_crtc_scaling_mode_fixup()
1736 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; in radeon_crtc_scaling_mode_fixup()
1737 if (radeon_encoder->underscan_vborder != 0) in radeon_crtc_scaling_mode_fixup()
1738 radeon_crtc->v_border = radeon_encoder->underscan_vborder; in radeon_crtc_scaling_mode_fixup()
1740 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; in radeon_crtc_scaling_mode_fixup()
1741 radeon_crtc->rmx_type = RMX_FULL; in radeon_crtc_scaling_mode_fixup()
1742 src_v = crtc->mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1743 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); in radeon_crtc_scaling_mode_fixup()
1744 src_h = crtc->mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1745 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); in radeon_crtc_scaling_mode_fixup()
1749 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { in radeon_crtc_scaling_mode_fixup()
1761 if (radeon_crtc->rmx_type != RMX_OFF) { in radeon_crtc_scaling_mode_fixup()
1765 radeon_crtc->vsc.full = dfixed_div(a, b); in radeon_crtc_scaling_mode_fixup()
1768 radeon_crtc->hsc.full = dfixed_div(a, b); in radeon_crtc_scaling_mode_fixup()
1770 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
1771 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
1794 * \param *stime Target location for timestamp taken immediately before
1796 * \param *etime Target location for timestamp taken immediately after
1801 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1822 struct radeon_device *rdev = dev->dev_private; in radeon_get_crtc_scanoutpos()
1885 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ in radeon_get_crtc_scanoutpos()
1931 vbl_start = mode->crtc_vdisplay; in radeon_get_crtc_scanoutpos()
1938 *hpos = *vpos - vbl_start; in radeon_get_crtc_scanoutpos()
1952 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
1965 *vpos -= vbl_start; in radeon_get_crtc_scanoutpos()
1977 vtotal = mode->crtc_vtotal; in radeon_get_crtc_scanoutpos()
1978 *vpos = *vpos - vtotal; in radeon_get_crtc_scanoutpos()
1982 *vpos = *vpos - vbl_end; in radeon_get_crtc_scanoutpos()
1993 struct drm_device *dev = crtc->dev; in radeon_get_crtc_scanout_position()
1994 unsigned int pipe = crtc->index; in radeon_get_crtc_scanout_position()