1021 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1083 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1085 		track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;  in r600_cs_check_reg()
1104 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1213 			ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1244 			ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1280 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1283 		track->cb_color_bo_mc[tmp] = reloc->gpu_offset;  in r600_cs_check_reg()
1294 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1296 		track->db_bo_mc = reloc->gpu_offset;  in r600_cs_check_reg()
1307 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1376 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1385 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1671 		offset = reloc->gpu_offset +  in r600_packet3_check()
1712 		offset = reloc->gpu_offset +  in r600_packet3_check()
1764 			offset = reloc->gpu_offset +  in r600_packet3_check()
1804 			offset = reloc->gpu_offset + tmp;  in r600_packet3_check()
1834 			offset = reloc->gpu_offset + tmp;  in r600_packet3_check()
1860 			ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
1876 			offset = reloc->gpu_offset +  in r600_packet3_check()
1898 		offset = reloc->gpu_offset +  in r600_packet3_check()
1963 				base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
1977 				mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
2007 				offset64 = reloc->gpu_offset + offset;  in r600_packet3_check()
2117 			ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
2150 			offset += reloc->gpu_offset;  in r600_packet3_check()
2169 			offset += reloc->gpu_offset;  in r600_packet3_check()
2198 		offset += reloc->gpu_offset;  in r600_packet3_check()
2223 			offset += reloc->gpu_offset;  in r600_packet3_check()
2247 			offset += reloc->gpu_offset;  in r600_packet3_check()
2407 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2413 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2414 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2441 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2445 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2446 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2451 					ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2452 					ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2456 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2466 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2467 					ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2468 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2469 					ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2477 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2478 					ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2479 					ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2480 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;  in r600_dma_cs_parse()
2512 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2513 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in r600_dma_cs_parse()