2381 	u64 src_offset, dst_offset;  in r600_dma_cs_parse()  local
2404 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2405 				dst_offset <<= 8;  in r600_dma_cs_parse()
2410 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2411 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_dma_cs_parse()
2417 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2419 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2443 					dst_offset = radeon_get_ib_value(p, idx+5);  in r600_dma_cs_parse()
2444 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in r600_dma_cs_parse()
2454 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2455 					dst_offset <<= 8;  in r600_dma_cs_parse()
2463 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2464 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in r600_dma_cs_parse()
2474 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2475 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;  in r600_dma_cs_parse()
2489 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2491 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2505 			dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2506 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in r600_dma_cs_parse()
2507 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2509 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()