635 	struct radeon_bo_list *reloc;  in r300_packet0_check()  local
669 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
676 		track->cb[i].robj = reloc->robj;  in r300_packet0_check()
679 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
682 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
689 		track->zb.robj = reloc->robj;  in r300_packet0_check()
692 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
711 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
721 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
723 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
725 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
727 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
730 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
734 		track->textures[i].robj = reloc->robj;  in r300_packet0_check()
784 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
792 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
794 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
796 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
869 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
877 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
879 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
881 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
1084 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1091 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1126 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1133 		track->aa.robj = reloc->robj;  in r300_packet0_check()
1136 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1179 	struct radeon_bo_list *reloc;  in r300_packet3_check()  local
1195 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet3_check()
1201 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r300_packet3_check()
1202 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r300_packet3_check()