1267 	struct radeon_bo_list *reloc;  in r100_reloc_pitch_offset()  local
1270 	r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_reloc_pitch_offset()
1280 	tmp += (((u32)reloc->gpu_offset) >> 10);  in r100_reloc_pitch_offset()
1283 		if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r100_reloc_pitch_offset()
1285 		if (reloc->tiling_flags & RADEON_TILING_MICRO) {  in r100_reloc_pitch_offset()
1306 	struct radeon_bo_list *reloc;  in r100_packet3_load_vbpntr()  local
1323 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_load_vbpntr()
1331 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1334 		track->arrays[i + 0].robj = reloc->robj;  in r100_packet3_load_vbpntr()
1336 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_load_vbpntr()
1343 		ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1344 		track->arrays[i + 1].robj = reloc->robj;  in r100_packet3_load_vbpntr()
1349 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_load_vbpntr()
1357 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1358 		track->arrays[i + 0].robj = reloc->robj;  in r100_packet3_load_vbpntr()
1555 	struct radeon_bo_list *reloc;  in r100_packet0_check()  local
1588 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1595 		track->zb.robj = reloc->robj;  in r100_packet0_check()
1598 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1601 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1608 		track->cb[0].robj = reloc->robj;  in r100_packet0_check()
1611 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1617 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1625 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r100_packet0_check()
1627 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r100_packet0_check()
1632 			ib[idx] = tmp + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1634 			ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1635 		track->textures[i].robj = reloc->robj;  in r100_packet0_check()
1644 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1652 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1653 		track->textures[0].cube_info[i].robj = reloc->robj;  in r100_packet0_check()
1662 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1670 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1671 		track->textures[1].cube_info[i].robj = reloc->robj;  in r100_packet0_check()
1680 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1688 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1689 		track->textures[2].cube_info[i].robj = reloc->robj;  in r100_packet0_check()
1698 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1706 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r100_packet0_check()
1708 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r100_packet0_check()
1769 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1776 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1913 	struct radeon_bo_list *reloc;  in r100_packet3_check()  local
1929 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_check()
1935 		ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);  in r100_packet3_check()
1936 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r100_packet3_check()
1943 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_check()
1949 		ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);  in r100_packet3_check()
1953 		track->arrays[0].robj = reloc->robj;  in r100_packet3_check()