1615 						struct rv7xx_pl *pl,  in ni_populate_memory_timing_parameters()  argument
1622 		(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);  in ni_populate_memory_timing_parameters()
1625 	radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);  in ni_populate_memory_timing_parameters()
2309 					 struct rv7xx_pl *pl,  in ni_convert_power_level_to_smc()  argument
2321 		((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;  in ni_convert_power_level_to_smc()
2323 	ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);  in ni_convert_power_level_to_smc()
2329 	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&  in ni_convert_power_level_to_smc()
2336 		if (pl->mclk > pi->mclk_edc_enable_threshold)  in ni_convert_power_level_to_smc()
2338 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)  in ni_convert_power_level_to_smc()
2341 		level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);  in ni_convert_power_level_to_smc()
2344 			if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=  in ni_convert_power_level_to_smc()
2351 			if (pl->mclk > ni_pi->mclk_rtt_mode_threshold)  in ni_convert_power_level_to_smc()
2355 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,  in ni_convert_power_level_to_smc()
2360 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);  in ni_convert_power_level_to_smc()
2366 					pl->vddc, &level->vddc);  in ni_convert_power_level_to_smc()
2379 						pl->vddci, &level->vddci);  in ni_convert_power_level_to_smc()
2384 	ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);  in ni_convert_power_level_to_smc()
2958 						 struct rv7xx_pl *pl,  in ni_convert_mc_reg_table_entry_to_smc()  argument
2965 		if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in ni_convert_mc_reg_table_entry_to_smc()
3927 	struct rv7xx_pl *pl = &ps->performance_levels[index];  in ni_parse_pplib_clock_info()  local
3931 	pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);  in ni_parse_pplib_clock_info()
3932 	pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16;  in ni_parse_pplib_clock_info()
3933 	pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);  in ni_parse_pplib_clock_info()
3934 	pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;  in ni_parse_pplib_clock_info()
3936 	pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);  in ni_parse_pplib_clock_info()
3937 	pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI);  in ni_parse_pplib_clock_info()
3938 	pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags);  in ni_parse_pplib_clock_info()
3941 	if (pl->vddc == 0xff01) {  in ni_parse_pplib_clock_info()
3943 			pl->vddc = pi->max_vddc;  in ni_parse_pplib_clock_info()
3947 		pi->acpi_vddc = pl->vddc;  in ni_parse_pplib_clock_info()
3948 		eg_pi->acpi_vddci = pl->vddci;  in ni_parse_pplib_clock_info()
3957 		eg_pi->ulv.pl = pl;  in ni_parse_pplib_clock_info()
3960 	if (pi->min_vddc_in_table > pl->vddc)  in ni_parse_pplib_clock_info()
3961 		pi->min_vddc_in_table = pl->vddc;  in ni_parse_pplib_clock_info()
3963 	if (pi->max_vddc_in_table < pl->vddc)  in ni_parse_pplib_clock_info()
3964 		pi->max_vddc_in_table = pl->vddc;  in ni_parse_pplib_clock_info()
3970 		pl->mclk = rdev->clock.default_mclk;  in ni_parse_pplib_clock_info()
3971 		pl->sclk = rdev->clock.default_sclk;  in ni_parse_pplib_clock_info()
3972 		pl->vddc = vddc;  in ni_parse_pplib_clock_info()
3973 		pl->vddci = vddci;  in ni_parse_pplib_clock_info()
3978 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in ni_parse_pplib_clock_info()
3979 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in ni_parse_pplib_clock_info()
3980 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in ni_parse_pplib_clock_info()
3981 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in ni_parse_pplib_clock_info()
4286 	struct rv7xx_pl *pl;  in ni_dpm_print_power_state()  local
4293 		pl = &ps->performance_levels[i];  in ni_dpm_print_power_state()
4296 			       i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);  in ni_dpm_print_power_state()
4299 			       i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);  in ni_dpm_print_power_state()
4310 	struct rv7xx_pl *pl;  in ni_dpm_debugfs_print_current_performance_level()  local
4318 		pl = &ps->performance_levels[current_index];  in ni_dpm_debugfs_print_current_performance_level()
4321 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);  in ni_dpm_debugfs_print_current_performance_level()
4330 	struct rv7xx_pl *pl;  in ni_dpm_get_current_sclk()  local
4338 		pl = &ps->performance_levels[current_index];  in ni_dpm_get_current_sclk()
4339 		return pl->sclk;  in ni_dpm_get_current_sclk()
4348 	struct rv7xx_pl *pl;  in ni_dpm_get_current_mclk()  local
4356 		pl = &ps->performance_levels[current_index];  in ni_dpm_get_current_mclk()
4357 		return pl->mclk;  in ni_dpm_get_current_mclk()