Lines Matching full:pi
252 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi() local
254 return pi; in kv_get_pi()
334 struct kv_power_info *pi = kv_get_pi(rdev); in kv_do_enable_didt() local
337 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
346 if (pi->caps_db_ramping) { in kv_do_enable_didt()
355 if (pi->caps_td_ramping) { in kv_do_enable_didt()
364 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
376 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_didt() local
379 if (pi->caps_sq_ramping || in kv_enable_didt()
380 pi->caps_db_ramping || in kv_enable_didt()
381 pi->caps_td_ramping || in kv_enable_didt()
382 pi->caps_tcp_ramping) { in kv_enable_didt()
404 struct kv_power_info *pi = kv_get_pi(rdev);
406 if (pi->caps_cac) {
436 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_smc_cac() local
439 if (pi->caps_cac) { in kv_enable_smc_cac()
443 pi->cac_enabled = false; in kv_enable_smc_cac()
445 pi->cac_enabled = true; in kv_enable_smc_cac()
446 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
448 pi->cac_enabled = false; in kv_enable_smc_cac()
457 struct kv_power_info *pi = kv_get_pi(rdev); in kv_process_firmware_header() local
463 &tmp, pi->sram_end); in kv_process_firmware_header()
466 pi->dpm_table_start = tmp; in kv_process_firmware_header()
470 &tmp, pi->sram_end); in kv_process_firmware_header()
473 pi->soft_regs_start = tmp; in kv_process_firmware_header()
480 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_dpm_voltage_scaling() local
483 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
486 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
488 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
489 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
496 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_interval() local
499 pi->graphics_interval = 1; in kv_set_dpm_interval()
502 pi->dpm_table_start + in kv_set_dpm_interval()
504 &pi->graphics_interval, in kv_set_dpm_interval()
505 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
512 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_boot_state() local
516 pi->dpm_table_start + in kv_set_dpm_boot_state()
518 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
519 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
537 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_divider_value() local
546 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
547 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
607 struct kv_power_info *pi = kv_get_pi(rdev); in kv_convert_2bit_index_to_voltage() local
609 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
618 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_vid() local
620 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
621 pi->graphics_level[index].MinVddNb = in kv_set_vid()
629 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_at() local
631 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
639 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enable() local
641 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
699 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_sclk_t() local
703 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
704 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
707 pi->dpm_table_start + in kv_update_sclk_t()
710 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
717 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_bootup_state() local
723 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
724 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
728 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
732 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
737 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
738 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
742 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
750 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_auto_thermal_throttling() local
753 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
756 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
758 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
759 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
766 struct kv_power_info *pi = kv_get_pi(rdev); in kv_upload_dpm_settings() local
770 pi->dpm_table_start + in kv_upload_dpm_settings()
772 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
774 pi->sram_end); in kv_upload_dpm_settings()
780 pi->dpm_table_start + in kv_upload_dpm_settings()
782 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
783 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
795 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_clk_bypass() local
798 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
820 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_uvd_table() local
830 pi->uvd_level_count = 0; in kv_populate_uvd_table()
832 if (pi->high_voltage_t && in kv_populate_uvd_table()
833 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
836 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
837 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
838 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
840 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
842 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
849 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
855 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
857 pi->uvd_level_count++; in kv_populate_uvd_table()
861 pi->dpm_table_start + in kv_populate_uvd_table()
863 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
864 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
868 pi->uvd_interval = 1; in kv_populate_uvd_table()
871 pi->dpm_table_start + in kv_populate_uvd_table()
873 &pi->uvd_interval, in kv_populate_uvd_table()
874 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
879 pi->dpm_table_start + in kv_populate_uvd_table()
881 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
883 pi->sram_end); in kv_populate_uvd_table()
891 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_vce_table() local
901 pi->vce_level_count = 0; in kv_populate_vce_table()
903 if (pi->high_voltage_t && in kv_populate_vce_table()
904 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
907 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
908 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
910 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
917 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
919 pi->vce_level_count++; in kv_populate_vce_table()
923 pi->dpm_table_start + in kv_populate_vce_table()
925 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
927 pi->sram_end); in kv_populate_vce_table()
931 pi->vce_interval = 1; in kv_populate_vce_table()
934 pi->dpm_table_start + in kv_populate_vce_table()
936 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
938 pi->sram_end); in kv_populate_vce_table()
943 pi->dpm_table_start + in kv_populate_vce_table()
945 (u8 *)&pi->vce_level, in kv_populate_vce_table()
947 pi->sram_end); in kv_populate_vce_table()
954 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_samu_table() local
964 pi->samu_level_count = 0; in kv_populate_samu_table()
966 if (pi->high_voltage_t && in kv_populate_samu_table()
967 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
970 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
971 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
973 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
980 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
982 pi->samu_level_count++; in kv_populate_samu_table()
986 pi->dpm_table_start + in kv_populate_samu_table()
988 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
990 pi->sram_end); in kv_populate_samu_table()
994 pi->samu_interval = 1; in kv_populate_samu_table()
997 pi->dpm_table_start + in kv_populate_samu_table()
999 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1001 pi->sram_end); in kv_populate_samu_table()
1006 pi->dpm_table_start + in kv_populate_samu_table()
1008 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1010 pi->sram_end); in kv_populate_samu_table()
1020 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_acp_table() local
1030 pi->acp_level_count = 0; in kv_populate_acp_table()
1032 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1033 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1039 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1041 pi->acp_level_count++; in kv_populate_acp_table()
1045 pi->dpm_table_start + in kv_populate_acp_table()
1047 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1049 pi->sram_end); in kv_populate_acp_table()
1053 pi->acp_interval = 1; in kv_populate_acp_table()
1056 pi->dpm_table_start + in kv_populate_acp_table()
1058 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1060 pi->sram_end); in kv_populate_acp_table()
1065 pi->dpm_table_start + in kv_populate_acp_table()
1067 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1069 pi->sram_end); in kv_populate_acp_table()
1078 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dfs_bypass_settings() local
1084 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1085 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1087 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1089 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1091 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1093 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1095 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1097 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1099 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1104 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1105 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1106 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1108 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1110 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1112 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1114 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1116 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1118 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1120 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1134 struct kv_power_info *pi = kv_get_pi(rdev); in kv_reset_acp_boot_level() local
1136 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1143 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_current_ps() local
1145 pi->current_rps = *rps; in kv_update_current_ps()
1146 pi->current_ps = *new_ps; in kv_update_current_ps()
1147 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1154 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_requested_ps() local
1156 pi->requested_rps = *rps; in kv_update_requested_ps()
1157 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1158 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1163 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable_bapm() local
1166 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1188 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable() local
1234 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1337 struct kv_power_info *pi = kv_get_pi(rdev);
1339 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1340 (u8 *)&value, sizeof(u16), pi->sram_end);
1346 struct kv_power_info *pi = kv_get_pi(rdev);
1348 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1349 value, pi->sram_end);
1355 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_sclk_t() local
1357 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1362 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_fps_limits() local
1365 if (pi->caps_fps) { in kv_init_fps_limits()
1369 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1371 pi->dpm_table_start + in kv_init_fps_limits()
1373 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1374 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1377 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1380 pi->dpm_table_start + in kv_init_fps_limits()
1382 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1383 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1391 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_powergate_state() local
1393 pi->uvd_power_gated = false; in kv_init_powergate_state()
1394 pi->vce_power_gated = false; in kv_init_powergate_state()
1395 pi->samu_power_gated = false; in kv_init_powergate_state()
1396 pi->acp_power_gated = false; in kv_init_powergate_state()
1426 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_uvd_dpm() local
1434 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1436 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1438 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1439 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1445 pi->dpm_table_start + in kv_update_uvd_dpm()
1447 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1448 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1478 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_vce_dpm() local
1487 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1488 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1490 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1493 pi->dpm_table_start + in kv_update_vce_dpm()
1495 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1497 pi->sram_end); in kv_update_vce_dpm()
1501 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1504 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1519 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_samu_dpm() local
1525 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1526 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1528 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1531 pi->dpm_table_start + in kv_update_samu_dpm()
1533 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1535 pi->sram_end); in kv_update_samu_dpm()
1539 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1542 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1567 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_boot_level() local
1570 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1572 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1573 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1576 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1583 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_dpm() local
1589 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1590 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1592 pi->acp_boot_level = kv_get_acp_boot_level(rdev); in kv_update_acp_dpm()
1595 pi->dpm_table_start + in kv_update_acp_dpm()
1597 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1599 pi->sram_end); in kv_update_acp_dpm()
1603 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1606 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1614 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_uvd() local
1616 if (pi->uvd_power_gated == gate) in kv_dpm_powergate_uvd()
1619 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1622 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1627 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1630 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1642 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_vce() local
1644 if (pi->vce_power_gated == gate) in kv_dpm_powergate_vce()
1647 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1650 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1655 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1665 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_samu() local
1667 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1670 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1674 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1677 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1685 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_acp() local
1687 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1693 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1697 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1700 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1710 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_valid_clock_range() local
1716 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1718 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1719 pi->lowest_valid = i; in kv_set_valid_clock_range()
1724 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1728 pi->highest_valid = i; in kv_set_valid_clock_range()
1730 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1731 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1732 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1733 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1735 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1739 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1741 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1743 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1744 pi->lowest_valid = i; in kv_set_valid_clock_range()
1749 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1754 pi->highest_valid = i; in kv_set_valid_clock_range()
1756 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1758 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1759 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1761 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1763 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1772 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_dfs_bypass_settings() local
1776 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1778 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1780 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1782 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1785 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1794 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_nb_dpm() local
1798 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1801 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1804 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1807 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1840 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_pre_set_power_state() local
1847 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1848 &pi->current_rps); in kv_dpm_pre_set_power_state()
1855 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_set_power_state() local
1856 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1857 struct radeon_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1860 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1869 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1898 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1929 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_post_set_power_state() local
1930 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
1945 struct kv_power_info *pi = kv_get_pi(rdev);
1960 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1970 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_max_power_limits_table() local
1972 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
1973 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
1975 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
1978 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
1981 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2028 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_boot_state() local
2030 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2031 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2032 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2033 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2034 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2035 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2036 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2037 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2083 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_sleep_divider_id_from_clock() local
2092 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2106 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_high_voltage_limit() local
2113 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2115 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2122 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2125 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2127 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2143 struct kv_power_info *pi = kv_get_pi(rdev); in kv_apply_state_adjust_rules() local
2165 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2195 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2196 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2204 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2207 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2208 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2216 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2222 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2227 pi->battery_state = true; in kv_apply_state_adjust_rules()
2229 pi->battery_state = false; in kv_apply_state_adjust_rules()
2242 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2243 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2244 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2245 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2257 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enabled_for_throttle() local
2259 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2264 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_ds_divider() local
2268 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2271 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2272 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2274 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2282 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_nbps_level_settings() local
2289 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2293 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2294 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2295 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2296 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2299 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2302 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2303 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2306 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2307 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2309 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2310 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2312 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2313 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2314 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2315 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2318 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2319 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2320 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2321 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2324 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2325 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2326 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2327 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2328 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2336 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dpm_settings() local
2339 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2342 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2343 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2350 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_graphics_levels() local
2358 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2360 if (pi->high_voltage_t && in kv_init_graphics_levels()
2361 (pi->high_voltage_t < in kv_init_graphics_levels()
2367 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2370 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2372 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2376 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2378 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2380 if (pi->high_voltage_t && in kv_init_graphics_levels()
2381 pi->high_voltage_t < in kv_init_graphics_levels()
2387 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2389 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2399 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_new_levels() local
2403 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2419 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_enabled_levels() local
2422 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2434 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_nbps_index_settings() local
2440 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2491 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_sys_info_table() local
2508 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2509 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2510 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2513 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2515 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2517 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2519 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2520 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2525 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2527 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2530 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2532 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2537 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2540 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2544 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2577 struct kv_power_info *pi = kv_get_pi(rdev); in kv_patch_boot_state() local
2580 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2614 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_pplib_clock_info() local
2626 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2724 struct kv_power_info *pi; in kv_dpm_init() local
2727 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2728 if (pi == NULL) in kv_dpm_init()
2730 rdev->pm.dpm.priv = pi; in kv_dpm_init()
2741 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2743 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2747 pi->enable_nb_dpm = false; in kv_dpm_init()
2749 pi->enable_nb_dpm = true; in kv_dpm_init()
2751 pi->caps_power_containment = true; in kv_dpm_init()
2752 pi->caps_cac = true; in kv_dpm_init()
2753 pi->enable_didt = false; in kv_dpm_init()
2754 if (pi->enable_didt) { in kv_dpm_init()
2755 pi->caps_sq_ramping = true; in kv_dpm_init()
2756 pi->caps_db_ramping = true; in kv_dpm_init()
2757 pi->caps_td_ramping = true; in kv_dpm_init()
2758 pi->caps_tcp_ramping = true; in kv_dpm_init()
2761 pi->caps_sclk_ds = true; in kv_dpm_init()
2762 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2763 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2767 pi->bapm_enable = true; in kv_dpm_init()
2769 pi->bapm_enable = false; in kv_dpm_init()
2771 pi->bapm_enable = false; in kv_dpm_init()
2773 pi->bapm_enable = true; in kv_dpm_init()
2775 pi->voltage_drop_t = 0; in kv_dpm_init()
2776 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2777 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2778 pi->caps_uvd_pg = true; in kv_dpm_init()
2779 pi->caps_uvd_dpm = true; in kv_dpm_init()
2780 pi->caps_vce_pg = false; /* XXX true */ in kv_dpm_init()
2781 pi->caps_samu_pg = false; in kv_dpm_init()
2782 pi->caps_acp_pg = false; in kv_dpm_init()
2783 pi->caps_stable_p_state = false; in kv_dpm_init()
2796 pi->enable_dpm = true; in kv_dpm_init()
2804 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_debugfs_print_current_performance_level() local
2814 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2818 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2819 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2827 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_sclk() local
2836 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_get_current_sclk()
2843 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_mclk() local
2845 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_current_mclk()
2885 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_sclk() local
2886 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2896 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_mclk() local
2898 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()