Lines Matching +full:event +full:- +full:deep
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
70 struct drm_device *dev = encoder->dev; in evergreen_hdmi_update_acr()
71 struct radeon_device *rdev = dev->dev_private; in evergreen_hdmi_update_acr()
74 if (encoder->crtc) { in evergreen_hdmi_update_acr()
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in evergreen_hdmi_update_acr()
76 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr()
87 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
88 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
91 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
94 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
100 struct radeon_device *rdev = encoder->dev->dev_private; in dce4_afmt_write_latency_fields()
103 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in dce4_afmt_write_latency_fields()
104 if (connector->latency_present[1]) in dce4_afmt_write_latency_fields()
105 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | in dce4_afmt_write_latency_fields()
106 AUDIO_LIPSYNC(connector->audio_latency[1]); in dce4_afmt_write_latency_fields()
110 if (connector->latency_present[0]) in dce4_afmt_write_latency_fields()
111 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | in dce4_afmt_write_latency_fields()
112 AUDIO_LIPSYNC(connector->audio_latency[0]); in dce4_afmt_write_latency_fields()
122 struct radeon_device *rdev = encoder->dev->dev_private; in dce4_afmt_hdmi_write_speaker_allocation()
140 struct radeon_device *rdev = encoder->dev->dev_private; in dce4_afmt_dp_write_speaker_allocation()
159 struct radeon_device *rdev = encoder->dev->dev_private; in evergreen_hdmi_write_sad_regs()
178 int max_channels = -1; in evergreen_hdmi_write_sad_regs()
184 if (sad->format == eld_reg_to_type[i][1]) { in evergreen_hdmi_write_sad_regs()
185 if (sad->channels > max_channels) { in evergreen_hdmi_write_sad_regs()
186 value = MAX_CHANNELS(sad->channels) | in evergreen_hdmi_write_sad_regs()
187 DESCRIPTOR_BYTE_2(sad->byte2) | in evergreen_hdmi_write_sad_regs()
188 SUPPORTED_FREQUENCIES(sad->freq); in evergreen_hdmi_write_sad_regs()
189 max_channels = sad->channels; in evergreen_hdmi_write_sad_regs()
192 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in evergreen_hdmi_write_sad_regs()
193 stereo_freqs |= sad->freq; in evergreen_hdmi_write_sad_regs()
258 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); in dce4_hdmi_audio_set_dto()
284 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); in dce4_dp_audio_set_dto()
308 struct drm_device *dev = encoder->dev; in dce4_set_vbi_packet()
309 struct radeon_device *rdev = dev->dev_private; in dce4_set_vbi_packet()
319 struct drm_device *dev = encoder->dev; in dce4_hdmi_set_color_depth()
320 struct radeon_device *rdev = dev->dev_private; in dce4_hdmi_set_color_depth()
334 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", in dce4_hdmi_set_color_depth()
335 connector->name, bpc); in dce4_hdmi_set_color_depth()
340 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", in dce4_hdmi_set_color_depth()
341 connector->name); in dce4_hdmi_set_color_depth()
346 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", in dce4_hdmi_set_color_depth()
347 connector->name); in dce4_hdmi_set_color_depth()
356 struct drm_device *dev = encoder->dev; in dce4_set_audio_packet()
357 struct radeon_device *rdev = dev->dev_private; in dce4_set_audio_packet()
391 struct drm_device *dev = encoder->dev; in dce4_set_mute()
392 struct radeon_device *rdev = dev->dev_private; in dce4_set_mute()
402 struct drm_device *dev = encoder->dev; in evergreen_hdmi_enable()
403 struct radeon_device *rdev = dev->dev_private; in evergreen_hdmi_enable()
405 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in evergreen_hdmi_enable()
407 if (!dig || !dig->afmt) in evergreen_hdmi_enable()
414 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, in evergreen_hdmi_enable()
419 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
422 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, in evergreen_hdmi_enable()
425 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
429 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
431 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); in evergreen_hdmi_enable()
434 dig->afmt->enabled = enable; in evergreen_hdmi_enable()
437 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); in evergreen_hdmi_enable()
442 struct drm_device *dev = encoder->dev; in evergreen_dp_enable()
443 struct radeon_device *rdev = dev->dev_private; in evergreen_dp_enable()
445 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in evergreen_dp_enable()
448 if (!dig || !dig->afmt) in evergreen_dp_enable()
458 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
461 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, in evergreen_dp_enable()
464 if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { in evergreen_dp_enable()
465 dig_connector = radeon_connector->con_priv; in evergreen_dp_enable()
466 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); in evergreen_dp_enable()
469 if (dig_connector->dp_clock == 162000) in evergreen_dp_enable()
474 WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); in evergreen_dp_enable()
477 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, in evergreen_dp_enable()
483 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); in evergreen_dp_enable()
484 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
488 dig->afmt->enabled = enable; in evergreen_dp_enable()