2800 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2855 			r = r600_dma_cs_next_reloc(p, &src_reloc);  in evergreen_dma_cs_parse()
2873 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2875 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2884 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2886 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2896 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
2906 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2907 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2913 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2915 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2932 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2934 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2943 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2945 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2955 				ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2956 				ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2976 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2978 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2993 				ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2996 				ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3016 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3018 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3033 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3034 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3047 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3053 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3054 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3078 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3080 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3095 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3096 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3107 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3117 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3118 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3124 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3126 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3143 				ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3165 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3167 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3182 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3183 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()