Lines Matching refs:reloc
1097 struct radeon_bo_list *reloc; in evergreen_cs_handle_reg() local
1143 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1172 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1185 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1214 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1222 track->db_z_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1226 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1234 track->db_z_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1238 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1246 track->db_s_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1250 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1258 track->db_s_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1273 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1282 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1295 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1360 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1366 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1378 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1384 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1385 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1439 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1446 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1449 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1467 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1474 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1477 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1500 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1505 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1506 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1517 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1522 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1523 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1555 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1563 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1564 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1571 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1579 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1580 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1584 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1591 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1592 track->htile_bo = reloc->robj; in evergreen_cs_handle_reg()
1702 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1708 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1716 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1722 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1730 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1736 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1775 struct radeon_bo_list *reloc; in evergreen_packet3_check() local
1813 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1819 offset = reloc->gpu_offset + in evergreen_packet3_check()
1859 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1865 offset = reloc->gpu_offset + in evergreen_packet3_check()
1894 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1900 offset = reloc->gpu_offset + in evergreen_packet3_check()
1922 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1928 offset = reloc->gpu_offset + in evergreen_packet3_check()
2017 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2023 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2025 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2026 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2074 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2079 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2095 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2101 offset = reloc->gpu_offset + in evergreen_packet3_check()
2149 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2158 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2160 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2162 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2187 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2196 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2198 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2200 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2227 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2232 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2243 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2248 offset = reloc->gpu_offset + in evergreen_packet3_check()
2264 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2270 offset = reloc->gpu_offset + in evergreen_packet3_check()
2286 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2292 offset = reloc->gpu_offset + in evergreen_packet3_check()
2355 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2362 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_packet3_check()
2363 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
2366 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_packet3_check()
2377 texture = reloc->robj; in evergreen_packet3_check()
2378 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2392 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2397 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2398 mipmap = reloc->robj; in evergreen_packet3_check()
2411 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2418 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2421 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2424 offset64 = reloc->gpu_offset + offset; in evergreen_packet3_check()
2493 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2500 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2502 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2505 offset += reloc->gpu_offset; in evergreen_packet3_check()
2512 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2519 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2521 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2524 offset += reloc->gpu_offset; in evergreen_packet3_check()
2537 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2548 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2550 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2553 offset += reloc->gpu_offset; in evergreen_packet3_check()
2566 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2573 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2575 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2578 offset += reloc->gpu_offset; in evergreen_packet3_check()
2593 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2600 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2602 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2605 offset += reloc->gpu_offset; in evergreen_packet3_check()
2643 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2654 offset += reloc->gpu_offset; in evergreen_packet3_check()