Lines Matching refs:gpu_offset
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1505 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1522 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1563 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1579 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1591 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1708 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1722 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1736 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1819 offset = reloc->gpu_offset + in evergreen_packet3_check()
1865 offset = reloc->gpu_offset + in evergreen_packet3_check()
1900 offset = reloc->gpu_offset + in evergreen_packet3_check()
1928 offset = reloc->gpu_offset + in evergreen_packet3_check()
2025 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2026 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2079 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2101 offset = reloc->gpu_offset + in evergreen_packet3_check()
2158 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2196 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2232 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2248 offset = reloc->gpu_offset + in evergreen_packet3_check()
2270 offset = reloc->gpu_offset + in evergreen_packet3_check()
2292 offset = reloc->gpu_offset + in evergreen_packet3_check()
2378 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2397 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2424 offset64 = reloc->gpu_offset + offset; in evergreen_packet3_check()
2505 offset += reloc->gpu_offset; in evergreen_packet3_check()
2524 offset += reloc->gpu_offset; in evergreen_packet3_check()
2553 offset += reloc->gpu_offset; in evergreen_packet3_check()
2578 offset += reloc->gpu_offset; in evergreen_packet3_check()
2605 offset += reloc->gpu_offset; in evergreen_packet3_check()
2654 offset += reloc->gpu_offset; in evergreen_packet3_check()
2832 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2840 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2841 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2883 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2884 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2885 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2886 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2896 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2900 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2901 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2906 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2907 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2911 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2942 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2943 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2944 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2945 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2955 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2956 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2957 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2958 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2991 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2992 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2993 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2994 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2995 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2996 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3031 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3032 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3033 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3034 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3047 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3049 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3050 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3053 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3054 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3056 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3093 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3094 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3095 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3096 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3107 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3111 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3112 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3117 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3118 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3122 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3143 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3144 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3180 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3181 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3182 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3183 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3204 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3205 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()