7062 	cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7063 	cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7064 	cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7065 	cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7066 	cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7067 	cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7068 	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7069 	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7074 		cp_int_cntl |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7082 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7085 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7088 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7091 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7100 				cp_m2p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7103 				cp_m2p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7106 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7109 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7125 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7128 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7131 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7134 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7143 				cp_m2p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7146 				cp_m2p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7149 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7152 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()