816 			if (ps->performance_levels[i].mclk > max_limits->mclk)  in ci_apply_state_adjust_rules()
817 				ps->performance_levels[i].mclk = max_limits->mclk;  in ci_apply_state_adjust_rules()
818 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ci_apply_state_adjust_rules()
819 				ps->performance_levels[i].sclk = max_limits->sclk;  in ci_apply_state_adjust_rules()
826 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
827 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
829 		mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
830 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
840 	ps->performance_levels[0].sclk = sclk;  in ci_apply_state_adjust_rules()
841 	ps->performance_levels[0].mclk = mclk;  in ci_apply_state_adjust_rules()
843 	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)  in ci_apply_state_adjust_rules()
844 		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
847 		if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)  in ci_apply_state_adjust_rules()
848 			ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;  in ci_apply_state_adjust_rules()
850 		if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)  in ci_apply_state_adjust_rules()
851 			ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
2580 		    boot_state->performance_levels[0].sclk) {  in ci_populate_smc_initial_state()
2588 		    boot_state->performance_levels[0].mclk) {  in ci_populate_smc_initial_state()
3751 				  state->performance_levels[0].sclk,  in ci_trim_dpm_states()
3752 				  state->performance_levels[high_limit_count].sclk);  in ci_trim_dpm_states()
3756 				  state->performance_levels[0].mclk,  in ci_trim_dpm_states()
3757 				  state->performance_levels[high_limit_count].mclk);  in ci_trim_dpm_states()
3760 				state->performance_levels[0].pcie_gen,  in ci_trim_dpm_states()
3761 				state->performance_levels[0].pcie_lane,  in ci_trim_dpm_states()
3762 				state->performance_levels[high_limit_count].pcie_gen,  in ci_trim_dpm_states()
3763 				state->performance_levels[high_limit_count].pcie_lane);  in ci_trim_dpm_states()
3846 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3848 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3887 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
3888 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4790 		pcie_speed = state->performance_levels[i].pcie_gen;  in ci_get_maximum_link_speed()
5465 	struct ci_pl *pl = &ps->performance_levels[index];  in ci_parse_pplib_clock_info()
5951 		pl = &ps->performance_levels[i];  in ci_dpm_print_power_state()
5978 		return requested_state->performance_levels[0].sclk;  in ci_dpm_get_sclk()
5980 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()
5989 		return requested_state->performance_levels[0].mclk;  in ci_dpm_get_mclk()
5991 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()