2862 					   SMU7_Discrete_MemoryLevel *memory_level)  in ci_populate_single_memory_level()  argument
2871 						    memory_clock, &memory_level->MinVddc);  in ci_populate_single_memory_level()
2879 						    memory_clock, &memory_level->MinVddci);  in ci_populate_single_memory_level()
2887 						    memory_clock, &memory_level->MinMvdd);  in ci_populate_single_memory_level()
2892 	memory_level->MinVddcPhases = 1;  in ci_populate_single_memory_level()
2898 						      &memory_level->MinVddcPhases);  in ci_populate_single_memory_level()
2900 	memory_level->EnabledForThrottle = 1;  in ci_populate_single_memory_level()
2901 	memory_level->UpH = 0;  in ci_populate_single_memory_level()
2902 	memory_level->DownH = 100;  in ci_populate_single_memory_level()
2903 	memory_level->VoltageDownH = 0;  in ci_populate_single_memory_level()
2904 	memory_level->ActivityLevel = (u16)pi->mclk_activity_target;  in ci_populate_single_memory_level()
2906 	memory_level->StutterEnable = false;  in ci_populate_single_memory_level()
2907 	memory_level->StrobeEnable = false;  in ci_populate_single_memory_level()
2908 	memory_level->EdcReadEnable = false;  in ci_populate_single_memory_level()
2909 	memory_level->EdcWriteEnable = false;  in ci_populate_single_memory_level()
2910 	memory_level->RttEnable = false;  in ci_populate_single_memory_level()
2912 	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;  in ci_populate_single_memory_level()
2919 		memory_level->StutterEnable = true;  in ci_populate_single_memory_level()
2923 		memory_level->StrobeEnable = 1;  in ci_populate_single_memory_level()
2926 		memory_level->StrobeRatio =  in ci_populate_single_memory_level()
2927 			si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);  in ci_populate_single_memory_level()
2930 			memory_level->EdcReadEnable = true;  in ci_populate_single_memory_level()
2934 			memory_level->EdcWriteEnable = true;  in ci_populate_single_memory_level()
2936 		if (memory_level->StrobeEnable) {  in ci_populate_single_memory_level()
2946 		memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);  in ci_populate_single_memory_level()
2950 …ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s…  in ci_populate_single_memory_level()
2954 	memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);  in ci_populate_single_memory_level()
2955 	memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);  in ci_populate_single_memory_level()
2956 	memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);  in ci_populate_single_memory_level()
2957 	memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);  in ci_populate_single_memory_level()
2959 	memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);  in ci_populate_single_memory_level()
2960 	memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);  in ci_populate_single_memory_level()
2961 	memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);  in ci_populate_single_memory_level()
2962 	memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);  in ci_populate_single_memory_level()
2963 	memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);  in ci_populate_single_memory_level()
2964 	memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);  in ci_populate_single_memory_level()
2965 	memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);  in ci_populate_single_memory_level()
2966 	memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);  in ci_populate_single_memory_level()
2967 	memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);  in ci_populate_single_memory_level()
2968 	memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);  in ci_populate_single_memory_level()
2969 	memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);  in ci_populate_single_memory_level()