Lines Matching refs:dyn_state
268 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
270 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
272 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
273 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
276 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
278 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
279 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
280 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
282 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
283 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
323 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
405 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
422 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
423 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
657 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
731 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
812 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
1621 rdev->pm.dpm.dyn_state.cac_tdp_table;
2132 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2150 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2168 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2299 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2300 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2306 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2322 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2325 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2326 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2328 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2330 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2333 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2335 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2337 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2343 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2345 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2347 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2350 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2352 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2354 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2578 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2579 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2586 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2587 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2641 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2645 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2647 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2649 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2684 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2688 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2690 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2717 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2721 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2723 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2749 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2753 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2755 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2868 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2870 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2876 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2878 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
2884 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2886 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2896 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
3122 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3126 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3128 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3132 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3213 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3225 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3430 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3432 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3434 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3499 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3509 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3771 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3773 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3923 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
3925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
3930 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3931 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
3972 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
3974 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
3978 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3979 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
4005 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4011 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4012 … if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4036 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4038 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4042 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4043 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4069 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4073 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4089 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4906 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
4908 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4910 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4933 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
4935 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
4937 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4939 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
5052 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5054 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5056 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5058 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5060 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5062 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5064 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5066 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5068 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5070 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5072 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5074 &rdev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5655 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5772 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5776 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5780 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5781 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5782 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5783 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5784 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5785 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5786 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5787 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5788 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5790 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5791 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5792 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5794 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5795 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5796 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5797 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5916 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5917 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5918 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
5919 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()