Lines Matching refs:dpm
183 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
268 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
270 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
272 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
273 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
276 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
277 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
278 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
279 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
280 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
282 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
283 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
323 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
356 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
357 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
358 rdev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
359 rdev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
362 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
405 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
422 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
423 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
657 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
731 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
739 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
791 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
792 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
798 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
809 if (rdev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
812 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
814 if (rdev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
834 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
835 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
836 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
837 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
885 rdev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
886 rdev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
954 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
961 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
965 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
969 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
970 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
972 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
973 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
978 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
979 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
980 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
987 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
997 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
1013 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1032 rdev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1122 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1127 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1184 if (rdev->pm.dpm.fan.ucode_fan_control)
1217 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1249 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1333 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1435 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1621 rdev->pm.dpm.dyn_state.cac_tdp_table;
1980 if (rdev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
2000 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
2132 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2150 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2168 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2299 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2300 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2306 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2322 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2325 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2326 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2328 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2330 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2333 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2335 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2337 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2343 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2345 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2347 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2350 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2352 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2354 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2578 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2579 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2586 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2587 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2641 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2645 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2647 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2649 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2684 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2688 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2690 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2717 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2721 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2723 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2749 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2753 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2755 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2868 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2870 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2876 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2878 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
2884 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2886 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2896 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
2918 (rdev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
3111 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3122 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3126 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3128 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3132 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3213 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3225 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3430 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3432 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3434 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3499 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3509 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3544 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in ci_init_smc_table()
3557 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3560 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3771 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3773 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3877 if (rdev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
3878 rdev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
3922 if (rdev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
3923 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
3925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
3930 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3931 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
3971 if (rdev->pm.dpm.ac_power) in ci_enable_vce_dpm()
3972 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
3974 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
3978 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3979 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
4004 if (rdev->pm.dpm.ac_power)
4005 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4011 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4012 … if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4035 if (rdev->pm.dpm.ac_power)
4036 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4038 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4042 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4043 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4069 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4073 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4089 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4316 rdev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
4906 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
4908 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4910 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4933 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
4935 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
4937 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4939 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
5052 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5054 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5056 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5058 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5060 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5062 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5064 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5066 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5068 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5070 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5072 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5074 &rdev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5118 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5153 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_enable()
5308 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_disable()
5454 rdev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5456 rdev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5560 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in ci_parse_power_table()
5563 if (!rdev->pm.dpm.ps) in ci_parse_power_table()
5566 rdev->pm.dpm.num_ps = 0; in ci_parse_power_table()
5578 rdev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5579 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ci_parse_power_table()
5594 &rdev->pm.dpm.ps[i], k, in ci_parse_power_table()
5599 rdev->pm.dpm.num_ps = i + 1; in ci_parse_power_table()
5605 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5612 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5613 rdev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5650 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5651 kfree(rdev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5653 kfree(rdev->pm.dpm.ps); in ci_dpm_fini()
5654 kfree(rdev->pm.dpm.priv); in ci_dpm_fini()
5655 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5674 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5772 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5776 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5780 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5781 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5782 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5783 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5784 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5785 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5786 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5787 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5788 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5790 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5791 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5792 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5794 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5795 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5796 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5797 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5816 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5819 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5825 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5828 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5868 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
5874 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
5877 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
5883 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
5916 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5917 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5918 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
5919 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()