Lines Matching full:pi
183 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
185 return pi; in ci_get_pi()
197 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
207 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
213 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
217 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
221 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
231 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
235 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
237 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
238 pi->caps_cac = false; in ci_initialize_powertune_defaults()
239 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
240 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
241 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
242 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
244 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
245 pi->caps_cac = true; in ci_initialize_powertune_defaults()
247 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
249 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
250 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
251 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
262 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
263 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
264 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
265 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
291 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
292 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
295 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
298 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
299 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
306 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
307 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
309 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
310 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
311 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
312 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
319 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
320 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
324 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
325 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
327 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
334 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
335 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
342 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
343 pi->sram_end); in ci_populate_dw8()
347 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
354 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
361 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
369 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
370 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
371 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
393 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
394 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
401 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
402 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
403 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
410 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
411 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
418 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
419 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
420 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
431 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
433 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
466 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
470 if (pi->caps_power_containment) { in ci_populate_pm_base()
474 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
502 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
503 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
513 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
516 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
525 if (pi->caps_db_ramping) { in ci_do_enable_didt()
534 if (pi->caps_td_ramping) { in ci_do_enable_didt()
543 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
603 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
606 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
607 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
628 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
633 pi->power_containment_features = 0; in ci_enable_power_containment()
634 if (pi->caps_power_containment) { in ci_enable_power_containment()
635 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
640 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
643 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
648 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
651 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
661 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
668 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
669 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
672 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
675 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
677 pi->power_containment_features = 0; in ci_enable_power_containment()
686 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
690 if (pi->caps_cac) { in ci_enable_smc_cac()
695 pi->cac_enabled = false; in ci_enable_smc_cac()
697 pi->cac_enabled = true; in ci_enable_smc_cac()
699 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
701 pi->cac_enabled = false; in ci_enable_smc_cac()
711 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
714 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
729 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
737 if (pi->caps_power_containment) { in ci_power_control_set_level()
751 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
753 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
756 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
763 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
765 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
784 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
805 pi->battery_state = true; in ci_apply_state_adjust_rules()
807 pi->battery_state = false; in ci_apply_state_adjust_rules()
922 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
925 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
927 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
929 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
930 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
944 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
953 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1006 pi->fan_table_start, in ci_thermal_setup_fan_table()
1009 pi->sram_end); in ci_thermal_setup_fan_table()
1021 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1024 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1043 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1050 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1054 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1091 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1096 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1136 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1139 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1200 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1203 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1205 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1209 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1211 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1269 struct ci_power_info *pi = ci_get_pi(rdev);
1272 pi->soft_regs_start + reg_offset,
1273 value, pi->sram_end);
1280 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1283 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1284 value, pi->sram_end); in ci_write_smc_soft_register()
1289 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1290 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1292 if (pi->caps_fps) { in ci_init_fps_limits()
1305 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1309 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1310 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1313 pi->dpm_table_start + in ci_update_sclk_t()
1316 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1325 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1330 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1331 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1339 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1340 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1341 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1351 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1352 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1353 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1356 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1357 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1358 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1367 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1402 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1418 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1421 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1422 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1423 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1426 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1427 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1428 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1441 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1444 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1447 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1448 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1454 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1455 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1461 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1467 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1471 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1477 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1495 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1501 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1513 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1538 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1549 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1552 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1555 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1556 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1562 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1563 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1574 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1587 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1619 struct ci_power_info *pi = ci_get_pi(rdev);
1631 if (pi->caps_automatic_dc_transition) {
1685 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1687 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1699 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1701 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1713 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1715 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1727 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1729 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1803 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1810 &tmp, pi->sram_end); in ci_process_firmware_header()
1814 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1819 &tmp, pi->sram_end); in ci_process_firmware_header()
1823 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1828 &tmp, pi->sram_end); in ci_process_firmware_header()
1832 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1837 &tmp, pi->sram_end); in ci_process_firmware_header()
1841 pi->fan_table_start = tmp; in ci_process_firmware_header()
1846 &tmp, pi->sram_end); in ci_process_firmware_header()
1850 pi->arb_table_start = tmp; in ci_process_firmware_header()
1857 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1859 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1861 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1863 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1865 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1867 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1869 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1871 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1872 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1873 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1874 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1875 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1876 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1877 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1878 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1879 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1884 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1886 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1950 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1953 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1961 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2006 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
2010 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2080 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2092 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2121 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2124 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2127 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2130 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2133 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2138 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2140 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2142 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2145 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2148 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2151 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2156 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2158 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2160 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2163 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2166 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2169 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2174 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2176 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2206 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2209 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2212 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2215 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2217 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2230 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2232 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2235 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2238 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2240 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2252 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2255 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2258 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2261 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2263 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2298 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2301 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2400 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2404 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2405 &tmp, pi->sram_end); in ci_init_arb_table_index()
2412 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2413 tmp, pi->sram_end); in ci_init_arb_table_index()
2533 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2540 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2541 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2543 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2544 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2553 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2556 pi->sram_end); in ci_do_program_memory_timing_parameters()
2563 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2565 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2575 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2581 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2589 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2614 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2615 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2628 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2629 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2779 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2780 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2781 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2782 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2783 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2784 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2785 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2786 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2787 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2788 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2806 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2812 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2864 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2894 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2904 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2914 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2915 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2916 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2921 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2922 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2925 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2928 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2929 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2932 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2933 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2943 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2977 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2980 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2981 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2982 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2983 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2988 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2989 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2991 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2993 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3015 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3016 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3017 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3018 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3037 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3038 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3040 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3043 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3060 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3062 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3064 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3066 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3068 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3069 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3070 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3078 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3092 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3093 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3110 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3117 pi->ulv.supported = false; in ci_populate_ulv_level()
3121 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3135 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3148 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3150 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3151 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3152 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3153 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3172 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3205 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3223 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3239 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3263 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3264 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3265 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3269 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3277 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3278 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3282 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3284 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3287 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3289 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3290 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3295 pi->sram_end); in ci_populate_all_graphic_levels()
3310 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3311 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3312 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3316 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3326 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3331 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3335 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3336 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3337 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3338 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3341 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3343 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3344 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3347 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3352 pi->sram_end); in ci_populate_all_memory_levels()
3380 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3382 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3385 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3386 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3387 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3388 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3389 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3390 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3394 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3398 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3399 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3400 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3403 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3404 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3405 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3406 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3407 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3408 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3409 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3410 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3411 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3412 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3413 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3414 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3415 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3416 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3417 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3418 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3419 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3421 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3428 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3446 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3449 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3452 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3455 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3458 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3461 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3464 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3467 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3469 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3471 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3473 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3477 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3480 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3482 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3484 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3486 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3491 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3493 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3495 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3497 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3502 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3504 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3506 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3512 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3514 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3516 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3542 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3543 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3545 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3552 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3563 if (pi->mem_gddr5) in ci_init_smc_table()
3567 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3614 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3615 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3616 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3618 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3619 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3620 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3622 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3623 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3624 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3641 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3643 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3651 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3653 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3677 pi->dpm_table_start + in ci_init_smc_table()
3681 pi->sram_end); in ci_init_smc_table()
3707 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3708 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3738 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3750 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3755 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3802 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3807 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3808 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3811 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3817 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3818 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3821 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3827 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3828 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3831 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3843 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3845 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3847 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3851 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3859 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3866 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3875 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3879 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3885 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3889 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3892 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3895 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3898 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3901 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3907 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3918 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3928 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3932 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3934 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3941 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3943 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3944 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3945 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3948 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3951 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3952 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3953 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3956 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3967 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3977 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3980 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3982 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3989 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
4000 struct ci_power_info *pi = ci_get_pi(rdev);
4010 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4013 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4015 if (!pi->caps_samu_dpm)
4022 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4031 struct ci_power_info *pi = ci_get_pi(rdev);
4041 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4044 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4046 if (!pi->caps_acp_dpm)
4053 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4064 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4068 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4070 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4072 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4077 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4103 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4112 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4115 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4137 struct ci_power_info *pi = ci_get_pi(rdev);
4141 pi->smc_state_table.AcpBootLevel = 0;
4145 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4156 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4163 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4164 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4165 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4166 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4167 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4168 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4169 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4170 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4171 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4173 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4174 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4194 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4199 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4200 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4202 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4218 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4219 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4221 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4237 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4238 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4240 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4257 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4258 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4260 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4272 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4273 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4275 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4287 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4288 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4290 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4303 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4324 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4350 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4357 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4611 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4613 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4671 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4674 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4675 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4678 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4679 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4707 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4710 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4711 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4715 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4718 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4719 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4720 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4726 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4729 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4731 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4737 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4740 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4742 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4745 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4748 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4749 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4751 pi->sram_end); in ci_populate_initial_mc_reg_table()
4756 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4758 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4761 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4763 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4766 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4768 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4770 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4771 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4838 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4843 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4846 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4848 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4849 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4856 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4866 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4871 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4879 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4884 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4904 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4925 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4926 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4929 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4930 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4947 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4948 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4961 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4962 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5080 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5087 pi->mem_gddr5 = true; in ci_get_memory_type()
5089 pi->mem_gddr5 = false; in ci_get_memory_type()
5097 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5099 pi->current_rps = *rps; in ci_update_current_ps()
5100 pi->current_ps = *new_ps; in ci_update_current_ps()
5101 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5108 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5110 pi->requested_rps = *rps; in ci_update_requested_ps()
5111 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5112 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5117 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5123 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5130 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5131 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5152 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5158 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5166 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5169 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5171 if (pi->dynamic_ss) in ci_dpm_enable()
5173 if (pi->thermal_protection) in ci_dpm_enable()
5203 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5307 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5317 if (pi->thermal_protection) in ci_dpm_disable()
5338 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5339 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5340 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5344 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5373 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5395 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5463 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5475 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5476 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5479 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5483 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5487 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5488 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5489 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5494 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5495 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5496 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5497 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5502 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5503 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5504 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5505 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5506 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5507 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5508 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5509 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5510 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5513 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5514 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5515 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5516 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5517 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5518 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5519 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5520 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5521 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5666 struct ci_power_info *pi; in ci_dpm_init() local
5671 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5672 if (pi == NULL) in ci_dpm_init()
5674 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5679 pi->sys_pcie_mask = 0; in ci_dpm_init()
5682 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5686 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5689 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5691 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5693 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5694 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5695 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5696 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5698 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5699 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5700 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5701 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5703 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5727 pi->dll_default_on = false; in ci_dpm_init()
5728 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5730 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5731 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5732 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5733 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5734 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5735 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5736 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5737 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5739 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5741 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5742 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5743 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5744 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5749 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5752 pi->caps_sclk_ds = true; in ci_dpm_init()
5754 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5755 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5756 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5757 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5761 pi->caps_fps = false; in ci_dpm_init()
5763 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5765 pi->caps_uvd_dpm = true; in ci_dpm_init()
5766 pi->caps_vce_dpm = true; in ci_dpm_init()
5800 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5801 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5802 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5804 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5805 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5806 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5809 pi->uvd_enabled = false; in ci_dpm_init()
5811 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5860 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5861 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5862 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5864 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5866 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5870 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5872 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5879 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5881 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5886 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5889 pi->pcie_performance_request = in ci_dpm_init()
5892 pi->pcie_performance_request = false; in ci_dpm_init()
5897 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5898 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5899 pi->dynamic_ss = true; in ci_dpm_init()
5901 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5902 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5903 pi->dynamic_ss = true; in ci_dpm_init()
5907 pi->thermal_protection = true; in ci_dpm_init()
5909 pi->thermal_protection = false; in ci_dpm_init()
5911 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5913 pi->uvd_power_gated = false; in ci_dpm_init()
5921 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5929 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5930 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5934 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5974 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5975 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5985 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5986 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()