Lines Matching +full:pre +full:- +full:emphasis
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
90 struct drm_device *dev = chan->dev; in radeon_process_aux_ch()
91 struct radeon_device *rdev = dev->dev_private; in radeon_process_aux_ch()
100 mutex_lock(&chan->mutex); in radeon_process_aux_ch()
101 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); in radeon_process_aux_ch()
103 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); in radeon_process_aux_ch()
110 args.v1.ucChannelID = chan->rec.i2c_id; in radeon_process_aux_ch()
113 args.v2.ucHPD_ID = chan->rec.hpd; in radeon_process_aux_ch()
115 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); in radeon_process_aux_ch()
122 r = -ETIMEDOUT; in radeon_process_aux_ch()
129 r = -EIO; in radeon_process_aux_ch()
136 r = -EIO; in radeon_process_aux_ch()
149 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); in radeon_process_aux_ch()
150 mutex_unlock(&chan->mutex); in radeon_process_aux_ch()
168 if (WARN_ON(msg->size > 16)) in radeon_dp_aux_transfer_atom()
169 return -E2BIG; in radeon_dp_aux_transfer_atom()
171 tx_buf[0] = msg->address & 0xff; in radeon_dp_aux_transfer_atom()
172 tx_buf[1] = (msg->address >> 8) & 0xff; in radeon_dp_aux_transfer_atom()
173 tx_buf[2] = (msg->request << 4) | in radeon_dp_aux_transfer_atom()
174 ((msg->address >> 16) & 0xf); in radeon_dp_aux_transfer_atom()
175 tx_buf[3] = msg->size ? (msg->size - 1) : 0; in radeon_dp_aux_transfer_atom()
177 switch (msg->request & ~DP_AUX_I2C_MOT) { in radeon_dp_aux_transfer_atom()
186 if (WARN_ON_ONCE(msg->size > 12)) in radeon_dp_aux_transfer_atom()
187 return -E2BIG; in radeon_dp_aux_transfer_atom()
191 tx_size = HEADER_SIZE + msg->size; in radeon_dp_aux_transfer_atom()
192 if (msg->size == 0) in radeon_dp_aux_transfer_atom()
196 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); in radeon_dp_aux_transfer_atom()
201 ret = msg->size; in radeon_dp_aux_transfer_atom()
209 if (msg->size == 0) in radeon_dp_aux_transfer_atom()
214 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); in radeon_dp_aux_transfer_atom()
217 ret = -EINVAL; in radeon_dp_aux_transfer_atom()
222 msg->reply = ack >> 4; in radeon_dp_aux_transfer_atom()
229 struct drm_device *dev = radeon_connector->base.dev; in radeon_dp_aux_init()
230 struct radeon_device *rdev = dev->dev_private; in radeon_dp_aux_init()
233 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; in radeon_dp_aux_init()
234 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; in radeon_dp_aux_init()
237 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; in radeon_dp_aux_init()
239 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; in radeon_dp_aux_init()
241 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; in radeon_dp_aux_init()
244 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); in radeon_dp_aux_init()
246 radeon_connector->ddc_bus->has_aux = true; in radeon_dp_aux_init()
339 return -EINVAL; in radeon_dp_get_dp_link_config()
356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in radeon_dp_encoder_service()
362 struct drm_device *dev = radeon_connector->base.dev; in radeon_dp_getsinktype()
363 struct radeon_device *rdev = dev->dev_private; in radeon_dp_getsinktype()
366 radeon_connector->ddc_bus->rec.i2c_id, 0); in radeon_dp_getsinktype()
371 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; in radeon_dp_probe_oui()
374 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
377 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) in radeon_dp_probe_oui()
381 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) in radeon_dp_probe_oui()
388 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; in radeon_dp_getdpcd()
392 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, in radeon_dp_getdpcd()
395 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
397 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
398 dig_connector->dpcd); in radeon_dp_getdpcd()
405 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
412 struct drm_device *dev = encoder->dev; in radeon_dp_get_panel_mode()
413 struct radeon_device *rdev = dev->dev_private; in radeon_dp_get_panel_mode()
422 if (!radeon_connector->con_priv) in radeon_dp_get_panel_mode()
427 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, in radeon_dp_get_panel_mode()
437 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { in radeon_dp_get_panel_mode()
439 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, in radeon_dp_get_panel_mode()
456 if (!radeon_connector->con_priv) in radeon_dp_set_link_config()
458 dig_connector = radeon_connector->con_priv; in radeon_dp_set_link_config()
460 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || in radeon_dp_set_link_config()
461 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { in radeon_dp_set_link_config()
462 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
463 mode->clock, in radeon_dp_set_link_config()
464 &dig_connector->dp_lane_count, in radeon_dp_set_link_config()
465 &dig_connector->dp_clock); in radeon_dp_set_link_config()
467 dig_connector->dp_clock = 0; in radeon_dp_set_link_config()
468 dig_connector->dp_lane_count = 0; in radeon_dp_set_link_config()
481 if ((mode->clock > 340000) && in radeon_dp_mode_valid_helper()
485 if (!radeon_connector->con_priv) in radeon_dp_mode_valid_helper()
487 dig_connector = radeon_connector->con_priv; in radeon_dp_mode_valid_helper()
489 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
490 mode->clock, in radeon_dp_mode_valid_helper()
506 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; in radeon_dp_needs_link_train()
508 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) in radeon_dp_needs_link_train()
511 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) in radeon_dp_needs_link_train()
522 if (!radeon_connector->con_priv) in radeon_dp_set_rx_power_state()
525 dig_connector = radeon_connector->con_priv; in radeon_dp_set_rx_power_state()
528 if (dig_connector->dpcd[0] >= 0x11) { in radeon_dp_set_rx_power_state()
529 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, in radeon_dp_set_rx_power_state()
555 atombios_dig_transmitter_setup(dp_info->encoder, in radeon_dp_update_vs_emph()
557 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
560 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, in radeon_dp_update_vs_emph()
561 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
569 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { in radeon_dp_set_tp()
581 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); in radeon_dp_set_tp()
591 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, in radeon_dp_set_tp()
592 dp_info->dp_clock, dp_info->enc_id, rtp); in radeon_dp_set_tp()
596 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); in radeon_dp_set_tp()
601 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); in radeon_dp_link_train_init()
602 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in radeon_dp_link_train_init()
606 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); in radeon_dp_link_train_init()
609 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init()
610 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_init()
613 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_init()
616 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) in radeon_dp_link_train_init()
617 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); in radeon_dp_link_train_init()
620 tmp = dp_info->dp_lane_count; in radeon_dp_link_train_init()
621 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init()
623 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); in radeon_dp_link_train_init()
626 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); in radeon_dp_link_train_init()
627 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); in radeon_dp_link_train_init()
630 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) in radeon_dp_link_train_init()
631 atombios_dig_encoder_setup(dp_info->encoder, in radeon_dp_link_train_init()
634 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, in radeon_dp_link_train_init()
635 dp_info->dp_clock, dp_info->enc_id, 0); in radeon_dp_link_train_init()
638 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_init()
650 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_finish()
655 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) in radeon_dp_link_train_finish()
656 atombios_dig_encoder_setup(dp_info->encoder, in radeon_dp_link_train_finish()
659 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, in radeon_dp_link_train_finish()
660 dp_info->dp_clock, dp_info->enc_id, 0); in radeon_dp_link_train_finish()
672 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
679 dp_info->tries = 0; in radeon_dp_link_train_cr()
682 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); in radeon_dp_link_train_cr()
684 if (drm_dp_dpcd_read_link_status(dp_info->aux, in radeon_dp_link_train_cr()
685 dp_info->link_status) <= 0) { in radeon_dp_link_train_cr()
690 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { in radeon_dp_link_train_cr()
695 for (i = 0; i < dp_info->dp_lane_count; i++) { in radeon_dp_link_train_cr()
696 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
699 if (i == dp_info->dp_lane_count) { in radeon_dp_link_train_cr()
704 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
705 ++dp_info->tries; in radeon_dp_link_train_cr()
706 if (dp_info->tries == 5) { in radeon_dp_link_train_cr()
711 dp_info->tries = 0; in radeon_dp_link_train_cr()
713 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
716 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
722 return -1; in radeon_dp_link_train_cr()
724 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", in radeon_dp_link_train_cr()
725 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_cr()
726 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()
736 if (dp_info->tp3_supported) in radeon_dp_link_train_ce()
742 dp_info->tries = 0; in radeon_dp_link_train_ce()
745 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); in radeon_dp_link_train_ce()
747 if (drm_dp_dpcd_read_link_status(dp_info->aux, in radeon_dp_link_train_ce()
748 dp_info->link_status) <= 0) { in radeon_dp_link_train_ce()
753 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { in radeon_dp_link_train_ce()
759 if (dp_info->tries > 5) { in radeon_dp_link_train_ce()
765 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_ce()
768 dp_info->tries++; in radeon_dp_link_train_ce()
773 return -1; in radeon_dp_link_train_ce()
775 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", in radeon_dp_link_train_ce()
776 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_ce()
777 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in radeon_dp_link_train_ce()
786 struct drm_device *dev = encoder->dev; in radeon_dp_link_train()
787 struct radeon_device *rdev = dev->dev_private; in radeon_dp_link_train()
796 if (!radeon_encoder->enc_priv) in radeon_dp_link_train()
798 dig = radeon_encoder->enc_priv; in radeon_dp_link_train()
801 if (!radeon_connector->con_priv) in radeon_dp_link_train()
803 dig_connector = radeon_connector->con_priv; in radeon_dp_link_train()
805 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && in radeon_dp_link_train()
806 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) in radeon_dp_link_train()
815 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { in radeon_dp_link_train()
821 if (dig->dig_encoder) in radeon_dp_link_train()
825 if (dig->linkb) in radeon_dp_link_train()
830 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) in radeon_dp_link_train()
840 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
844 dp_info.dp_lane_count = dig_connector->dp_lane_count; in radeon_dp_link_train()
845 dp_info.dp_clock = dig_connector->dp_clock; in radeon_dp_link_train()
846 dp_info.aux = &radeon_connector->ddc_bus->aux; in radeon_dp_link_train()