1156 	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);  in dce4_crtc_do_set_base()  local
1205 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1213 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1221 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1228 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1236 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1244 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1254 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1263 		fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |  in dce4_crtc_do_set_base()
1266 		fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1404 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1477 	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;  in avivo_crtc_do_set_base()  local
1527 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1535 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1543 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1552 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1561 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1572 			fb_swap =  in avivo_crtc_do_set_base()
1578 		fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1625 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()