20 #define DSI_CMD2BKX_SEL			0xFF
23 #define DSI_CMD2_BK0_PVGAMCTRL		0xB0 /* Positive Voltage Gamma Control */
24 #define DSI_CMD2_BK0_NVGAMCTRL		0xB1 /* Negative Voltage Gamma Control */
25 #define DSI_CMD2_BK0_LNESET		0xC0 /* Display Line setting */
26 #define DSI_CMD2_BK0_PORCTRL		0xC1 /* Porch control */
27 #define DSI_CMD2_BK0_INVSEL		0xC2 /* Inversion selection, Frame Rate Control */
30 #define DSI_CMD2_BK1_VRHS		0xB0 /* Vop amplitude setting */
31 #define DSI_CMD2_BK1_VCOM		0xB1 /* VCOM amplitude setting */
32 #define DSI_CMD2_BK1_VGHSS		0xB2 /* VGH Voltage setting */
33 #define DSI_CMD2_BK1_TESTCMD		0xB3 /* TEST Command Setting */
34 #define DSI_CMD2_BK1_VGLS		0xB5 /* VGL Voltage setting */
35 #define DSI_CMD2_BK1_PWCTLR1		0xB7 /* Power Control 1 */
36 #define DSI_CMD2_BK1_PWCTLR2		0xB8 /* Power Control 2 */
37 #define DSI_CMD2_BK1_SPD1		0xC1 /* Source pre_drive timing set1 */
38 #define DSI_CMD2_BK1_SPD2		0xC2 /* Source EQ2 Setting */
39 #define DSI_CMD2_BK1_MIPISET1		0xD0 /* MIPI Setting 1 */
44  * BIT[4, 0]: [CN2, BKXSEL]
49 #define DSI_CMD2BK1_SEL			0x11
50 #define DSI_CMD2BK0_SEL			0x10
51 #define DSI_CMD2BKX_SEL_NONE		0x00
54 #define DSI_LINESET_LINE		0x69
56 #define DSI_LINESET_LINEDELTA		GENMASK(1, 0)
60 #define DSI_INVSEL_NLINV		GENMASK(2, 0)
68 #define DSI_CMD2_BK1_VRHA_SET		0x45
69 #define DSI_CMD2_BK1_VCOM_SET		0x13
70 #define DSI_CMD2_BK1_VGHSS_SET		GENMASK(2, 0)
73 #define DSI_VGLS_SEL			GENMASK(2, 0)
77 #define DSI_PWCTLR1_APOS		BIT(0) /* Source OP output bias, min */
81 #define DSI_PWCTLR2_AVCL		0x0    /* AVCL -4.4v */
130 	ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);  in st7701_init_sequence()
135 	ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);  in st7701_init_sequence()
141 		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL);  in st7701_init_sequence()
142 	ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,  in st7701_init_sequence()
143 		   0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12,  in st7701_init_sequence()
144 		   0x2B, 0x34, 0x1F);  in st7701_init_sequence()
145 	ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,  in st7701_init_sequence()
146 		   0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E,  in st7701_init_sequence()
147 		   0x2C, 0x34, 0x1F);  in st7701_init_sequence()
158 			0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL);  in st7701_init_sequence()
174 	ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);  in st7701_init_sequence()
175 	ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,  in st7701_init_sequence()
176 		   0x00, 0x00, 0x44, 0x44);  in st7701_init_sequence()
177 	ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,  in st7701_init_sequence()
178 		   0x00, 0x65, 0x00, 0x67, 0x00, 0x00);  in st7701_init_sequence()
179 	ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);  in st7701_init_sequence()
180 	ST7701_DSI(st7701, 0xE4, 0x44, 0x44);  in st7701_init_sequence()
181 	ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,  in st7701_init_sequence()
182 		   0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);  in st7701_init_sequence()
183 	ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);  in st7701_init_sequence()
184 	ST7701_DSI(st7701, 0xE7, 0x44, 0x44);  in st7701_init_sequence()
185 	ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,  in st7701_init_sequence()
186 		   0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);  in st7701_init_sequence()
187 	ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);  in st7701_init_sequence()
188 	ST7701_DSI(st7701, 0xEC, 0x00, 0x00);  in st7701_init_sequence()
189 	ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,  in st7701_init_sequence()
190 		   0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);  in st7701_init_sequence()
194 		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);  in st7701_init_sequence()
202 	gpiod_set_value(st7701->reset, 0);  in st7701_prepare()
206 	if (ret < 0)  in st7701_prepare()
215 	return 0;  in st7701_prepare()
222 	ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);  in st7701_enable()
224 	return 0;  in st7701_enable()
231 	ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);  in st7701_disable()
233 	return 0;  in st7701_disable()
240 	ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);  in st7701_unprepare()
244 	gpiod_set_value(st7701->reset, 0);  in st7701_unprepare()
259 	return 0;  in st7701_unprepare()
349 	for (i = 0; i < desc->num_supplies; i++)  in st7701_dsi_probe()
354 	if (ret < 0)  in st7701_dsi_probe()
397 	return 0;  in st7701_dsi_remove()