Lines Matching refs:DSI_CLK_CTRL
62 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) macro
1253 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
1256 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor()
1264 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk()
1271 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk()
1291 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1294 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { in dsi_pll_power()
1552 DUMPREG(DSI_CLK_CTRL); in dsi_dump_dsi_regs()
2082 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ in dsi_cio_init()
2106 REG_FLD_MOD(dsi, DSI_CLK_CTRL, in dsi_cio_init()
2117 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ in dsi_cio_init()
2132 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); in dsi_cio_uninit()
3052 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) { in dsi_enter_ulps()
3054 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); in dsi_enter_ulps()
3401 r = dsi_read_reg(dsi, DSI_CLK_CTRL); in dsi_config_cmd_mode_interleaving()