39 	return (nvkm_rd32(device, 0x00154c) & 0x1) + 1;  in g84_pcie_version()
46 	nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0));  in g84_pcie_set_version()
53 	nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0);  in g84_pcie_set_cap_speed()
59 	u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000;  in g84_pcie_cur_speed()
61 	case 0x30000:  in g84_pcie_cur_speed()
63 	case 0x20000:  in g84_pcie_cur_speed()
65 	case 0x10000:  in g84_pcie_cur_speed()
74 	u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300;  in g84_pcie_max_speed()
75 	if (reg_v == 0x2200)  in g84_pcie_max_speed()
86 		mask_value = 0x20;  in g84_pcie_set_link_speed()
88 		mask_value = 0x10;  in g84_pcie_set_link_speed()
90 	nvkm_pci_mask(pci, 0x460, 0x30, mask_value);  in g84_pcie_set_link_speed()
91 	nvkm_pci_mask(pci, 0x460, 0x1, 0x1);  in g84_pcie_set_link_speed()
99 	return 0;  in g84_pcie_set_link()
113 	 * Apparently, 0x041c stores some limit on the number of requests  in g84_pci_init()
119 	if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)  in g84_pci_init()
120 		nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);  in g84_pci_init()
122 		nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);  in g84_pci_init()
130 	return 0;  in g84_pcie_init()