32 	/* 0x01: no bank swizzle  in nv50_mmu_kind()
33 	 * 0x02: bank swizzled  in nv50_mmu_kind()
34 	 * 0x7f: invalid  in nv50_mmu_kind()
36 	 * 0x01/0x02 are values understood by the VRAM allocator,  in nv50_mmu_kind()
42 		0x01, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x00 */  in nv50_mmu_kind()
43 		0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,  in nv50_mmu_kind()
44 		0x01, 0x01, 0x01, 0x01, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x10 */  in nv50_mmu_kind()
45 		0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f, 0x7f, 0x7f,  in nv50_mmu_kind()
46 		0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x20 */  in nv50_mmu_kind()
47 		0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f,  in nv50_mmu_kind()
48 		0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x30 */  in nv50_mmu_kind()
49 		0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,  in nv50_mmu_kind()
50 		0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, /* 0x40 */  in nv50_mmu_kind()
51 		0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f,  in nv50_mmu_kind()
52 		0x7f, 0x7f, 0x7f, 0x7f, 0x01, 0x01, 0x01, 0x7f, /* 0x50 */  in nv50_mmu_kind()
53 		0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,  in nv50_mmu_kind()
54 		0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x60 */  in nv50_mmu_kind()
55 		0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02,  in nv50_mmu_kind()
56 		0x01, 0x7f, 0x02, 0x7f, 0x01, 0x7f, 0x02, 0x7f, /* 0x70 */  in nv50_mmu_kind()
57 		0x01, 0x01, 0x02, 0x02, 0x01, 0x01, 0x7f, 0x7f  in nv50_mmu_kind()
60 	*invalid = 0x7f;  in nv50_mmu_kind()
68 	.mem = {{ -1,  0, NVIF_CLASS_MEM_NV50}, nv50_mem_new, nv50_mem_map },
69 	.vmm = {{ -1, -1, NVIF_CLASS_VMM_NV50}, nv50_vmm_new, false, 0x1400 },