34 	nvkm_wr32(device, 0x17e8cc, start);  in gf100_ltc_cbc_clear()
35 	nvkm_wr32(device, 0x17e8d0, limit);  in gf100_ltc_cbc_clear()
36 	nvkm_wr32(device, 0x17e8c8, 0x00000004);  in gf100_ltc_cbc_clear()
44 	for (c = 0; c < ltc->ltc_nr; c++) {  in gf100_ltc_cbc_wait()
45 		for (s = 0; s < ltc->lts_nr; s++) {  in gf100_ltc_cbc_wait()
46 			const u32 addr = 0x1410c8 + (c * 0x2000) + (s * 0x400);  in gf100_ltc_cbc_wait()
59 	nvkm_mask(device, 0x17ea44, 0x0000000f, i);  in gf100_ltc_zbc_clear_color()
60 	nvkm_wr32(device, 0x17ea48, color[0]);  in gf100_ltc_zbc_clear_color()
61 	nvkm_wr32(device, 0x17ea4c, color[1]);  in gf100_ltc_zbc_clear_color()
62 	nvkm_wr32(device, 0x17ea50, color[2]);  in gf100_ltc_zbc_clear_color()
63 	nvkm_wr32(device, 0x17ea54, color[3]);  in gf100_ltc_zbc_clear_color()
70 	nvkm_mask(device, 0x17ea44, 0x0000000f, i);  in gf100_ltc_zbc_clear_depth()
71 	nvkm_wr32(device, 0x17ea58, depth);  in gf100_ltc_zbc_clear_depth()
76 	{ 0x00000001, "IDLE_ERROR_IQ" },
77 	{ 0x00000002, "IDLE_ERROR_CBC" },
78 	{ 0x00000004, "IDLE_ERROR_TSTG" },
79 	{ 0x00000008, "IDLE_ERROR_DSTG" },
80 	{ 0x00000010, "EVICTED_CB" },
81 	{ 0x00000020, "ILLEGAL_COMPSTAT" },
82 	{ 0x00000040, "BLOCKLINEAR_CB" },
83 	{ 0x00000100, "ECC_SEC_ERROR" },
84 	{ 0x00000200, "ECC_DED_ERROR" },
85 	{ 0x00000400, "DEBUG" },
86 	{ 0x00000800, "ATOMIC_TO_Z" },
87 	{ 0x00001000, "ILLEGAL_ATOMIC" },
88 	{ 0x00002000, "BLKACTIVITY_ERR" },
97 	u32 base = 0x141000 + (c * 0x2000) + (s * 0x400);  in gf100_ltc_lts_intr()
98 	u32 intr = nvkm_rd32(device, base + 0x020);  in gf100_ltc_lts_intr()
99 	u32 stat = intr & 0x0000ffff;  in gf100_ltc_lts_intr()
107 	nvkm_wr32(device, base + 0x020, intr);  in gf100_ltc_lts_intr()
116 	mask = nvkm_rd32(device, 0x00017c);  in gf100_ltc_intr()
119 		for (s = 0; s < ltc->lts_nr; s++)  in gf100_ltc_intr()
131 	nvkm_wr32(device, 0x70004, 0x00000001);  in gf100_ltc_invalidate()
132 	taken = nvkm_wait_msec(device, 2000, 0x70004, 0x00000003, 0x00000000);  in gf100_ltc_invalidate()
134 	if (taken > 0)  in gf100_ltc_invalidate()
144 	nvkm_wr32(device, 0x70010, 0x00000001);  in gf100_ltc_flush()
145 	taken = nvkm_wait_msec(device, 2000, 0x70010, 0x00000003, 0x00000000);  in gf100_ltc_flush()
147 	if (taken > 0)  in gf100_ltc_flush()
159 	u32 bits = (nvkm_rd32(device, 0x100c80) & 0x00001000) ? 16 : 17;  in gf100_ltc_oneinit_tag_ram()
165 		ltc->num_tags = 0;  in gf100_ltc_oneinit_tag_ram()
175 	tag_align = ltc->ltc_nr * 0x800;  in gf100_ltc_oneinit_tag_ram()
176 	tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align;  in gf100_ltc_oneinit_tag_ram()
178 	/* 4 part 4 sub: 0x2000 bytes for 56 tags */  in gf100_ltc_oneinit_tag_ram()
179 	/* 3 part 4 sub: 0x6000 bytes for 168 tags */  in gf100_ltc_oneinit_tag_ram()
182 	 * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags.  in gf100_ltc_oneinit_tag_ram()
186 	tag_size  = (ltc->num_tags / 64) * 0x6000 + tag_margin;  in gf100_ltc_oneinit_tag_ram()
189 	ret = nvkm_ram_get(device, NVKM_RAM_MM_NORMAL, 0x01, 12, tag_size,  in gf100_ltc_oneinit_tag_ram()
192 		ltc->num_tags = 0;  in gf100_ltc_oneinit_tag_ram()
204 	return nvkm_mm_init(&fb->tags, 0, 0, ltc->num_tags, 1);  in gf100_ltc_oneinit_tag_ram()
211 	const u32 parts = nvkm_rd32(device, 0x022438);  in gf100_ltc_oneinit()
212 	const u32  mask = nvkm_rd32(device, 0x022554);  in gf100_ltc_oneinit()
213 	const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28;  in gf100_ltc_oneinit()
216 	for (i = 0; i < parts; i++) {  in gf100_ltc_oneinit()
229 	u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);  in gf100_ltc_init()
231 	nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */  in gf100_ltc_init()
232 	nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);  in gf100_ltc_init()
233 	nvkm_wr32(device, 0x17e8d4, ltc->tag_base);  in gf100_ltc_init()
234 	nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);  in gf100_ltc_init()