Lines Matching full:device
36 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv40_gr_units()
47 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align, in nv40_gr_object_bind()
79 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in nv40_gr_chan_bind()
84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); in nv40_gr_chan_bind()
97 struct nvkm_device *device = subdev->device; in nv40_gr_chan_fini() local
101 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); in nv40_gr_chan_fini()
103 if (nvkm_rd32(device, 0x40032c) == inst) { in nv40_gr_chan_fini()
105 nvkm_wr32(device, 0x400720, 0x00000000); in nv40_gr_chan_fini()
106 nvkm_wr32(device, 0x400784, inst); in nv40_gr_chan_fini()
107 nvkm_mask(device, 0x400310, 0x00000020, 0x00000020); in nv40_gr_chan_fini()
108 nvkm_mask(device, 0x400304, 0x00000001, 0x00000001); in nv40_gr_chan_fini()
109 if (nvkm_msec(device, 2000, in nv40_gr_chan_fini()
110 if (!(nvkm_rd32(device, 0x400300) & 0x00000001)) in nv40_gr_chan_fini()
113 u32 insn = nvkm_rd32(device, 0x400308); in nv40_gr_chan_fini()
119 nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000); in nv40_gr_chan_fini()
122 if (nvkm_rd32(device, 0x400330) == inst) in nv40_gr_chan_fini()
123 nvkm_mask(device, 0x400330, 0x01000000, 0x00000000); in nv40_gr_chan_fini()
125 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); in nv40_gr_chan_fini()
176 struct nvkm_device *device = gr->base.engine.subdev.device; in nv40_gr_tile() local
177 struct nvkm_fifo *fifo = device->fifo; in nv40_gr_tile()
183 switch (device->chipset) { in nv40_gr_tile()
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
195 switch (device->chipset) { in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
205 nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
214 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
215 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
216 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
217 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
218 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
219 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
220 nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
221 nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
237 struct nvkm_device *device = subdev->device; in nv40_gr_intr() local
238 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); in nv40_gr_intr()
239 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); in nv40_gr_intr()
240 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); in nv40_gr_intr()
241 u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff; in nv40_gr_intr()
242 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); in nv40_gr_intr()
245 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); in nv40_gr_intr()
246 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; in nv40_gr_intr()
263 nvkm_mask(device, 0x402000, 0, 0); in nv40_gr_intr()
267 nvkm_wr32(device, NV03_PGRAPH_INTR, stat); in nv40_gr_intr()
268 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); in nv40_gr_intr()
290 struct nvkm_device *device = gr->base.engine.subdev.device; in nv40_gr_init() local
295 ret = nv40_grctx_init(device, &gr->size); in nv40_gr_init()
300 nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); in nv40_gr_init()
302 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv40_gr_init()
303 nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv40_gr_init()
305 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv40_gr_init()
306 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv40_gr_init()
307 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv40_gr_init()
308 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055); in nv40_gr_init()
309 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv40_gr_init()
310 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); in nv40_gr_init()
312 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); in nv40_gr_init()
313 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); in nv40_gr_init()
315 j = nvkm_rd32(device, 0x1540) & 0xff; in nv40_gr_init()
319 nvkm_wr32(device, 0x405000, i); in nv40_gr_init()
322 if (device->chipset == 0x40) { in nv40_gr_init()
323 nvkm_wr32(device, 0x4009b0, 0x83280fff); in nv40_gr_init()
324 nvkm_wr32(device, 0x4009b4, 0x000000a0); in nv40_gr_init()
326 nvkm_wr32(device, 0x400820, 0x83280eff); in nv40_gr_init()
327 nvkm_wr32(device, 0x400824, 0x000000a0); in nv40_gr_init()
330 switch (device->chipset) { in nv40_gr_init()
333 nvkm_wr32(device, 0x4009b8, 0x0078e366); in nv40_gr_init()
334 nvkm_wr32(device, 0x4009bc, 0x0000014c); in nv40_gr_init()
339 nvkm_wr32(device, 0x400828, 0x007596ff); in nv40_gr_init()
340 nvkm_wr32(device, 0x40082c, 0x00000108); in nv40_gr_init()
343 nvkm_wr32(device, 0x400828, 0x0072cb77); in nv40_gr_init()
344 nvkm_wr32(device, 0x40082c, 0x00000108); in nv40_gr_init()
351 nvkm_wr32(device, 0x400860, 0); in nv40_gr_init()
352 nvkm_wr32(device, 0x400864, 0); in nv40_gr_init()
357 nvkm_wr32(device, 0x400828, 0x07830610); in nv40_gr_init()
358 nvkm_wr32(device, 0x40082c, 0x0000016A); in nv40_gr_init()
364 nvkm_wr32(device, 0x400b38, 0x2ffff800); in nv40_gr_init()
365 nvkm_wr32(device, 0x400b3c, 0x00006000); in nv40_gr_init()
368 switch (device->chipset) { in nv40_gr_init()
371 nvkm_wr32(device, 0x400bc4, 0x1003d888); in nv40_gr_init()
372 nvkm_wr32(device, 0x400bbc, 0xb7a7b500); in nv40_gr_init()
375 nvkm_wr32(device, 0x400bc4, 0x0000e024); in nv40_gr_init()
376 nvkm_wr32(device, 0x400bbc, 0xb7a7b520); in nv40_gr_init()
381 nvkm_wr32(device, 0x400bc4, 0x1003d888); in nv40_gr_init()
382 nvkm_wr32(device, 0x400bbc, 0xb7a7b540); in nv40_gr_init()
389 vramsz = device->func->resource_size(device, 1) - 1; in nv40_gr_init()
390 switch (device->chipset) { in nv40_gr_init()
392 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
393 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
394 nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
395 nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
396 nvkm_wr32(device, 0x400820, 0); in nv40_gr_init()
397 nvkm_wr32(device, 0x400824, 0); in nv40_gr_init()
398 nvkm_wr32(device, 0x400864, vramsz); in nv40_gr_init()
399 nvkm_wr32(device, 0x400868, vramsz); in nv40_gr_init()
402 switch (device->chipset) { in nv40_gr_init()
410 nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
411 nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
414 nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
415 nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
418 nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
419 nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
420 nvkm_wr32(device, 0x400840, 0); in nv40_gr_init()
421 nvkm_wr32(device, 0x400844, 0); in nv40_gr_init()
422 nvkm_wr32(device, 0x4008A0, vramsz); in nv40_gr_init()
423 nvkm_wr32(device, 0x4008A4, vramsz); in nv40_gr_init()
431 nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, in nv40_gr_new_() argument
441 return nvkm_gr_ctor(func, device, index, true, &gr->base); in nv40_gr_new_()
473 nv40_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) in nv40_gr_new() argument
475 return nv40_gr_new_(&nv40_gr, device, index, pgr); in nv40_gr_new()