Lines Matching refs:lt
46 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay) in nvkm_dp_train_sense() argument
48 struct nvkm_dp *dp = lt->dp; in nvkm_dp_train_sense()
56 ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6); in nvkm_dp_train_sense()
61 ret = nvkm_rdaux(dp->aux, DPCD_LS0C, <->pc2stat, 1); in nvkm_dp_train_sense()
63 lt->pc2stat = 0x00; in nvkm_dp_train_sense()
65 lt->stat, lt->pc2stat); in nvkm_dp_train_sense()
67 OUTP_TRACE(&dp->outp, "status %6ph", lt->stat); in nvkm_dp_train_sense()
74 nvkm_dp_train_drive(struct lt_state *lt, bool pc) in nvkm_dp_train_drive() argument
76 struct nvkm_dp *dp = lt->dp; in nvkm_dp_train_drive()
86 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; in nvkm_dp_train_drive()
87 u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3; in nvkm_dp_train_drive()
104 lt->conf[i] = (lpre << 3) | lvsw; in nvkm_dp_train_drive()
105 lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); in nvkm_dp_train_drive()
108 i, lt->conf[i], lpc2); in nvkm_dp_train_drive()
126 ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4); in nvkm_dp_train_drive()
131 ret = nvkm_wraux(dp->aux, DPCD_LC0F, lt->pc2conf, 2); in nvkm_dp_train_drive()
140 nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern) in nvkm_dp_train_pattern() argument
142 struct nvkm_dp *dp = lt->dp; in nvkm_dp_train_pattern()
155 nvkm_dp_train_eq(struct lt_state *lt) in nvkm_dp_train_eq() argument
160 if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
161 nvkm_dp_train_pattern(lt, 3); in nvkm_dp_train_eq()
163 nvkm_dp_train_pattern(lt, 2); in nvkm_dp_train_eq()
167 nvkm_dp_train_drive(lt, lt->pc2)) || in nvkm_dp_train_eq()
168 nvkm_dp_train_sense(lt, lt->pc2, 400)) in nvkm_dp_train_eq()
171 eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); in nvkm_dp_train_eq()
172 for (i = 0; i < lt->dp->outp.ior->dp.nr && eq_done; i++) { in nvkm_dp_train_eq()
173 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in nvkm_dp_train_eq()
186 nvkm_dp_train_cr(struct lt_state *lt) in nvkm_dp_train_cr() argument
189 int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; in nvkm_dp_train_cr()
192 nvkm_dp_train_pattern(lt, 1); in nvkm_dp_train_cr()
195 if (nvkm_dp_train_drive(lt, false) || in nvkm_dp_train_cr()
196 nvkm_dp_train_sense(lt, false, 100)) in nvkm_dp_train_cr()
200 for (i = 0; i < lt->dp->outp.ior->dp.nr; i++) { in nvkm_dp_train_cr()
201 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in nvkm_dp_train_cr()
204 if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED) in nvkm_dp_train_cr()
210 if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { in nvkm_dp_train_cr()
211 voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; in nvkm_dp_train_cr()
226 struct lt_state lt = { in nvkm_dp_train_links() local
239 lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
242 if ((lnkcmp = lt.dp->info.lnkcmp)) { in nvkm_dp_train_links()
282 memset(lt.stat, 0x00, sizeof(lt.stat)); in nvkm_dp_train_links()
283 ret = nvkm_dp_train_cr(<); in nvkm_dp_train_links()
285 ret = nvkm_dp_train_eq(<); in nvkm_dp_train_links()
286 nvkm_dp_train_pattern(<, 0); in nvkm_dp_train_links()
405 ior->dp.mst = dp->lt.mst; in nvkm_dp_train()
418 atomic_set(&dp->lt.done, 1); in nvkm_dp_train()
441 atomic_set(&dp->lt.done, 0); in nvkm_dp_release()
471 dataKBps, linkKBps, ior->dp.mst, dp->lt.mst); in nvkm_dp_acquire()
472 if (linkKBps < dataKBps || ior->dp.mst != dp->lt.mst) { in nvkm_dp_acquire()
502 if (retrain || !atomic_read(&dp->lt.done)) in nvkm_dp_acquire()
531 atomic_set(&dp->lt.done, 0); in nvkm_dp_enable()
546 if (atomic_read(&dp->lt.done)) in nvkm_dp_hpd()
675 atomic_set(&dp->lt.done, 0); in nvkm_dp_ctor()