Lines Matching +full:pll1 +full:- +full:refclk
4 * Copyright 2007-2009 Stuart Bennett
92 if (drm->client.device.info.chipset == 0x11) { in NVSetOwner()
103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ in NVSetOwner()
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
152 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { in nouveau_hw_decode_pll()
153 pllvals->M1 &= 0xf; /* only 4 bits */ in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
168 struct nvif_object *device = &drm->client.device.object; in nouveau_hw_get_pllvals()
169 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); in nouveau_hw_get_pllvals()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
176 return -ENOENT; in nouveau_hw_get_pllvals()
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { in nouveau_hw_get_pllvals()
199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); in nouveau_hw_get_pllvals()
200 pllvals->refclk = pll_lim.refclk; in nouveau_hw_get_pllvals()
208 if (!pv->M1 || !pv->M2) in nouveau_hw_pllvals_to_clk()
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
221 domain = pci_domain_nr(dev->pdev->bus); in nouveau_hw_get_clock()
224 (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { in nouveau_hw_get_clock()
235 (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { in nouveau_hw_get_clock()
260 struct nvif_device *device = &drm->client.device; in nouveau_hw_fix_bad_vpll()
282 clk->pll_prog(clk, pll_lim.reg, &pv); in nouveau_hw_fix_bad_vpll()
299 nv04_display(dev)->saved_vga_font[plane][i] = in nouveau_vga_font_io()
302 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], in nouveau_vga_font_io()
330 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); in nouveau_hw_save_vga_fonts()
381 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); in rd_cio_state()
388 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
396 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ramdac()
399 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) in nv_save_state_ramdac()
400 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); in nv_save_state_ramdac()
402 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); in nv_save_state_ramdac()
403 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); in nv_save_state_ramdac()
405 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv_save_state_ramdac()
406 if (drm->client.device.info.chipset == 0x11) in nv_save_state_ramdac()
407 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
409 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); in nv_save_state_ramdac()
412 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); in nv_save_state_ramdac()
413 if (drm->client.device.info.chipset >= 0x30) in nv_save_state_ramdac()
414 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); in nv_save_state_ramdac()
416 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); in nv_save_state_ramdac()
417 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); in nv_save_state_ramdac()
418 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); in nv_save_state_ramdac()
419 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); in nv_save_state_ramdac()
420 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); in nv_save_state_ramdac()
421 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); in nv_save_state_ramdac()
422 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); in nv_save_state_ramdac()
423 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); in nv_save_state_ramdac()
427 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
428 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); in nv_save_state_ramdac()
432 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); in nv_save_state_ramdac()
434 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); in nv_save_state_ramdac()
435 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); in nv_save_state_ramdac()
439 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); in nv_save_state_ramdac()
440 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); in nv_save_state_ramdac()
444 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & in nv_save_state_ramdac()
447 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); in nv_save_state_ramdac()
448 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); in nv_save_state_ramdac()
450 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); in nv_save_state_ramdac()
453 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); in nv_save_state_ramdac()
455 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { in nv_save_state_ramdac()
456 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); in nv_save_state_ramdac()
457 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); in nv_save_state_ramdac()
458 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); in nv_save_state_ramdac()
461 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, in nv_save_state_ramdac()
471 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); in nv_load_state_ramdac()
472 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ramdac()
476 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) in nv_load_state_ramdac()
477 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); in nv_load_state_ramdac()
479 clk->pll_prog(clk, pllreg, ®p->pllvals); in nv_load_state_ramdac()
480 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); in nv_load_state_ramdac()
482 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); in nv_load_state_ramdac()
483 if (drm->client.device.info.chipset == 0x11) in nv_load_state_ramdac()
484 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); in nv_load_state_ramdac()
486 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); in nv_load_state_ramdac()
489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); in nv_load_state_ramdac()
490 if (drm->client.device.info.chipset >= 0x30) in nv_load_state_ramdac()
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); in nv_load_state_ramdac()
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); in nv_load_state_ramdac()
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); in nv_load_state_ramdac()
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); in nv_load_state_ramdac()
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); in nv_load_state_ramdac()
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); in nv_load_state_ramdac()
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); in nv_load_state_ramdac()
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); in nv_load_state_ramdac()
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); in nv_load_state_ramdac()
505 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()
506 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); in nv_load_state_ramdac()
510 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); in nv_load_state_ramdac()
512 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); in nv_load_state_ramdac()
513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); in nv_load_state_ramdac()
517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); in nv_load_state_ramdac()
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); in nv_load_state_ramdac()
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); in nv_load_state_ramdac()
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); in nv_load_state_ramdac()
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); in nv_load_state_ramdac()
525 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); in nv_load_state_ramdac()
527 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { in nv_load_state_ramdac()
528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); in nv_load_state_ramdac()
529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); in nv_load_state_ramdac()
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); in nv_load_state_ramdac()
534 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); in nv_load_state_ramdac()
542 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_vga()
545 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); in nv_save_state_vga()
552 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); in nv_save_state_vga()
556 regp->Graphics[i] = NVReadVgaGr(dev, head, i); in nv_save_state_vga()
559 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); in nv_save_state_vga()
566 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_vga()
569 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); in nv_load_state_vga()
572 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); in nv_load_state_vga()
580 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); in nv_load_state_vga()
584 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); in nv_load_state_vga()
593 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ext()
608 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) in nv_save_state_ext()
611 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) in nv_save_state_ext()
620 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { in nv_save_state_ext()
621 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); in nv_save_state_ext()
622 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); in nv_save_state_ext()
624 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) in nv_save_state_ext()
625 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); in nv_save_state_ext()
627 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) in nv_save_state_ext()
628 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); in nv_save_state_ext()
631 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); in nv_save_state_ext()
632 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); in nv_save_state_ext()
635 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); in nv_save_state_ext()
639 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { in nv_save_state_ext()
652 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); in nv_save_state_ext()
660 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); in nv_save_state_ext()
668 struct nvif_object *device = &drm->client.device.object; in nv_load_state_ext()
669 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ext()
673 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { in nv_load_state_ext()
679 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); in nv_load_state_ext()
685 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); in nv_load_state_ext()
686 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); in nv_load_state_ext()
687 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); in nv_load_state_ext()
688 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); in nv_load_state_ext()
691 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); in nv_load_state_ext()
692 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); in nv_load_state_ext()
693 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); in nv_load_state_ext()
695 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) in nv_load_state_ext()
696 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); in nv_load_state_ext()
698 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { in nv_load_state_ext()
699 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); in nv_load_state_ext()
702 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) in nv_load_state_ext()
709 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); in nv_load_state_ext()
721 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) in nv_load_state_ext()
724 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) in nv_load_state_ext()
731 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) in nv_load_state_ext()
737 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { in nv_load_state_ext()
745 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { in nv_load_state_ext()
748 nvif_msec(&drm->client.device, 650, in nv_load_state_ext()
752 nvif_msec(&drm->client.device, 650, in nv_load_state_ext()
763 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); in nv_load_state_ext()
771 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); in nv_load_state_ext()
778 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; in nv_save_state_palette()
786 state->crtc_reg[head].DAC[i] = nvif_rd08(device, in nv_save_state_palette()
797 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; in nouveau_hw_load_state_palette()
806 state->crtc_reg[head].DAC[i]); in nouveau_hw_load_state_palette()
817 if (drm->client.device.info.chipset == 0x11) in nouveau_hw_save_state()