288 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];  in nv04_dfp_mode_set()  local
301 	regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;  in nv04_dfp_mode_set()
302 	regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;  in nv04_dfp_mode_set()
306 		regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;  in nv04_dfp_mode_set()
308 		regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;  in nv04_dfp_mode_set()
309 	regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;  in nv04_dfp_mode_set()
310 	regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;  in nv04_dfp_mode_set()
311 	regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;  in nv04_dfp_mode_set()
312 	regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;  in nv04_dfp_mode_set()
314 	regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;  in nv04_dfp_mode_set()
315 	regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;  in nv04_dfp_mode_set()
316 	regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;  in nv04_dfp_mode_set()
317 	regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;  in nv04_dfp_mode_set()
318 	regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;  in nv04_dfp_mode_set()
319 	regp->fp_vert_regs[FP_VALID_START] = 0;  in nv04_dfp_mode_set()
320 	regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;  in nv04_dfp_mode_set()
323 	regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |  in nv04_dfp_mode_set()
328 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;  in nv04_dfp_mode_set()
330 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;  in nv04_dfp_mode_set()
334 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;  in nv04_dfp_mode_set()
337 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;  in nv04_dfp_mode_set()
339 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;  in nv04_dfp_mode_set()
341 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;  in nv04_dfp_mode_set()
344 		regp->fp_control |= (2 << 24);  in nv04_dfp_mode_set()
356 			regp->fp_control |= (8 << 28);  in nv04_dfp_mode_set()
359 		regp->fp_control |= (8 << 28);  in nv04_dfp_mode_set()
361 	regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |  in nv04_dfp_mode_set()
370 	regp->fp_debug_1 = 0;  in nv04_dfp_mode_set()
372 	regp->fp_debug_2 = 0;  in nv04_dfp_mode_set()
390 			regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |  in nv04_dfp_mode_set()
396 			regp->fp_horiz_regs[FP_VALID_START] += diff / 2;  in nv04_dfp_mode_set()
397 			regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;  in nv04_dfp_mode_set()
406 			regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |  in nv04_dfp_mode_set()
412 			regp->fp_vert_regs[FP_VALID_START] += diff / 2;  in nv04_dfp_mode_set()
413 			regp->fp_vert_regs[FP_VALID_END] -= diff / 2;  in nv04_dfp_mode_set()
422 			regp->dither = savep->dither | 0x00010000;  in nv04_dfp_mode_set()
425 			regp->dither = savep->dither | 0x00000001;  in nv04_dfp_mode_set()
427 				regp->dither_regs[i] = 0xe4e4e4e4;  in nv04_dfp_mode_set()
428 				regp->dither_regs[i + 3] = 0x44444444;  in nv04_dfp_mode_set()
436 				regp->dither_regs[i] = savep->dither_regs[i];  in nv04_dfp_mode_set()
437 				regp->dither_regs[i + 3] = savep->dither_regs[i + 3];  in nv04_dfp_mode_set()
440 		regp->dither = savep->dither;  in nv04_dfp_mode_set()
443 	regp->fp_margin_color = 0;  in nv04_dfp_mode_set()