270 	DBG("VCO freq: %llu", pd.vco_freq);  in pll_calculate()
271 	DBG("fdata: %llu", fdata);  in pll_calculate()
272 	DBG("pix_clk: %lu", pix_clk);  in pll_calculate()
273 	DBG("tmds clk: %llu", tmds_clk);  in pll_calculate()
274 	DBG("HSCLK_SEL: %d", pd.hsclk_divsel);  in pll_calculate()
275 	DBG("DEC_START: %llu", dec_start);  in pll_calculate()
276 	DBG("DIV_FRAC_START: %llu", frac_start);  in pll_calculate()
277 	DBG("PLL_CPCTRL: %u", cpctrl);  in pll_calculate()
278 	DBG("PLL_RCTRL: %u", rctrl);  in pll_calculate()
279 	DBG("PLL_CCTRL: %u", cctrl);  in pll_calculate()
280 	DBG("INTEGLOOP_GAIN: %u", integloop_gain);  in pll_calculate()
281 	DBG("TX_BAND: %d", pd.tx_band_sel);  in pll_calculate()
282 	DBG("PLL_CMP: %u", pll_cmp);  in pll_calculate()
361 	DBG("com_svs_mode_clk_sel = 0x%x", cfg->com_svs_mode_clk_sel);  in pll_calculate()
362 	DBG("com_hsclk_sel = 0x%x", cfg->com_hsclk_sel);  in pll_calculate()
363 	DBG("com_lock_cmp_en = 0x%x", cfg->com_lock_cmp_en);  in pll_calculate()
364 	DBG("com_pll_cctrl_mode0 = 0x%x", cfg->com_pll_cctrl_mode0);  in pll_calculate()
365 	DBG("com_pll_rctrl_mode0 = 0x%x", cfg->com_pll_rctrl_mode0);  in pll_calculate()
366 	DBG("com_cp_ctrl_mode0 = 0x%x", cfg->com_cp_ctrl_mode0);  in pll_calculate()
367 	DBG("com_dec_start_mode0 = 0x%x", cfg->com_dec_start_mode0);  in pll_calculate()
368 	DBG("com_div_frac_start1_mode0 = 0x%x", cfg->com_div_frac_start1_mode0);  in pll_calculate()
369 	DBG("com_div_frac_start2_mode0 = 0x%x", cfg->com_div_frac_start2_mode0);  in pll_calculate()
370 	DBG("com_div_frac_start3_mode0 = 0x%x", cfg->com_div_frac_start3_mode0);  in pll_calculate()
371 	DBG("com_integloop_gain0_mode0 = 0x%x", cfg->com_integloop_gain0_mode0);  in pll_calculate()
372 	DBG("com_integloop_gain1_mode0 = 0x%x", cfg->com_integloop_gain1_mode0);  in pll_calculate()
373 	DBG("com_lock_cmp1_mode0 = 0x%x", cfg->com_lock_cmp1_mode0);  in pll_calculate()
374 	DBG("com_lock_cmp2_mode0 = 0x%x", cfg->com_lock_cmp2_mode0);  in pll_calculate()
375 	DBG("com_lock_cmp3_mode0 = 0x%x", cfg->com_lock_cmp3_mode0);  in pll_calculate()
376 	DBG("com_core_clk_en = 0x%x", cfg->com_core_clk_en);  in pll_calculate()
377 	DBG("com_coreclk_div = 0x%x", cfg->com_coreclk_div);  in pll_calculate()
378 	DBG("phy_mode = 0x%x", cfg->phy_mode);  in pll_calculate()
380 	DBG("tx_l0_lane_mode = 0x%x", cfg->tx_lx_lane_mode[0]);  in pll_calculate()
381 	DBG("tx_l2_lane_mode = 0x%x", cfg->tx_lx_lane_mode[2]);  in pll_calculate()
384 		DBG("tx_l%d_tx_band = 0x%x", i, cfg->tx_lx_tx_band[i]);  in pll_calculate()
385 		DBG("tx_l%d_tx_drv_lvl = 0x%x", i, cfg->tx_lx_tx_drv_lvl[i]);  in pll_calculate()
386 		DBG("tx_l%d_tx_emp_post1_lvl = 0x%x", i,  in pll_calculate()
388 		DBG("tx_l%d_vmode_ctrl1 = 0x%x", i, cfg->tx_lx_vmode_ctrl1[i]);  in pll_calculate()
389 		DBG("tx_l%d_vmode_ctrl2 = 0x%x", i, cfg->tx_lx_vmode_ctrl2[i]);  in pll_calculate()
412 	DBG("Disabling PHY");  in hdmi_8996_pll_set_clk_rate()
550 	DBG("Waiting for PHY ready");  in hdmi_8996_phy_ready_status()
562 	DBG("PHY is %sready", phy_ready ? "" : "*not* ");  in hdmi_8996_phy_ready_status()
574 	DBG("Waiting for PLL lock");  in hdmi_8996_pll_lock_status()
587 	DBG("HDMI PLL is %slocked", pll_locked ? "" : "*not* ");  in hdmi_8996_pll_lock_status()