10 #define S_DIV_ROUND_UP(n, d)	\  argument
11 	(((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
129 	timing->ta_go = 3;  in msm_dsi_dphy_timing_calc()
133 	DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc()
168 	timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;  in msm_dsi_dphy_timing_calc_v2()
177 	ui_x8 = ui << 3;  in msm_dsi_dphy_timing_calc_v2()
185 	temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;  in msm_dsi_dphy_timing_calc_v2()
186 	tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;  in msm_dsi_dphy_timing_calc_v2()
190 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v2()
192 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v2()
201 	temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;  in msm_dsi_dphy_timing_calc_v2()
202 	tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;  in msm_dsi_dphy_timing_calc_v2()
206 	tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v2()
208 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v2()
227 	temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;  in msm_dsi_dphy_timing_calc_v2()
228 	temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;  in msm_dsi_dphy_timing_calc_v2()
229 	temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :  in msm_dsi_dphy_timing_calc_v2()
230 				(((timing->hs_rqst_ckln << 3) + 8) * ui);  in msm_dsi_dphy_timing_calc_v2()
243 	timing->ta_go = 3;  in msm_dsi_dphy_timing_calc_v2()
247 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc_v2()
285 	ui_x8 = ui << 3;  in msm_dsi_dphy_timing_calc_v3()
293 	temp = 300 * coeff - (timing->clk_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v3()
298 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v3()
300 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v3()
309 	temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v3()
335 	temp = 8 * ui + (timing->clk_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v3()
336 	temp += (((timing->clk_zero + 3) << 3) + 11) * ui;  in msm_dsi_dphy_timing_calc_v3()
337 	temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :  in msm_dsi_dphy_timing_calc_v3()
338 		(((timing->hs_rqst_ckln << 3) + 8) * ui);  in msm_dsi_dphy_timing_calc_v3()
351 	timing->ta_go = 3;  in msm_dsi_dphy_timing_calc_v3()
355 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc_v3()
391 	ui_x8 = ui << 3;  in msm_dsi_dphy_timing_calc_v4()
404 	temp = 300 * coeff - (timing->clk_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v4()
409 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v4()
411 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v4()
420 	temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v4()
455 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc_v4()
495 				      "%s: failed to init regulator, ret=%d\n",  in dsi_phy_regulator_init()
535 					"regulator %d set op mode failed, %d\n",  in dsi_phy_regulator_enable()
544 		DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);  in dsi_phy_regulator_enable()
565 		DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);  in dsi_phy_enable_resource()
679 		DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",  in dsi_phy_driver_probe()
780 		DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",  in msm_dsi_phy_enable()
787 		DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",  in msm_dsi_phy_enable()
794 		DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);  in msm_dsi_phy_enable()
807 			DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",  in msm_dsi_phy_enable()