194 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)  in dsi_write()  function
799 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);  in dsi_intr_ctrl()
846 		dsi_write(msm_host, REG_DSI_CTRL, 0);  in dsi_ctrl_config()
867 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);  in dsi_ctrl_config()
871 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);  in dsi_ctrl_config()
876 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);  in dsi_ctrl_config()
883 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);  in dsi_ctrl_config()
886 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,  in dsi_ctrl_config()
899 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);  in dsi_ctrl_config()
903 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);  in dsi_ctrl_config()
908 		dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,  in dsi_ctrl_config()
914 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);  in dsi_ctrl_config()
917 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);  in dsi_ctrl_config()
921 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_ctrl_config()
928 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
933 		dsi_write(msm_host, REG_DSI_LANE_CTRL,  in dsi_ctrl_config()
939 	dsi_write(msm_host, REG_DSI_CTRL, data);  in dsi_ctrl_config()
975 		dsi_write(msm_host, REG_DSI_ACTIVE_H,  in dsi_timing_setup()
978 		dsi_write(msm_host, REG_DSI_ACTIVE_V,  in dsi_timing_setup()
981 		dsi_write(msm_host, REG_DSI_TOTAL,  in dsi_timing_setup()
985 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,  in dsi_timing_setup()
988 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);  in dsi_timing_setup()
989 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,  in dsi_timing_setup()
996 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,  in dsi_timing_setup()
1003 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,  in dsi_timing_setup()
1011 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset()
1014 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset()
1016 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset()
1041 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);  in dsi_op_mode_config()
1055 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);  in dsi_set_tx_power_mode()
1412 	dsi_write(msm_host, REG_DSI_CTRL, data1);  in dsi_sw_reset_restore()
1419 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset_restore()
1423 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset_restore()
1425 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset_restore()
1427 	dsi_write(msm_host, REG_DSI_CTRL, data0);  in dsi_sw_reset_restore()
1463 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);  in dsi_ack_err_status()
1465 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);  in dsi_ack_err_status()
1477 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);  in dsi_timeout_status()
1493 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);  in dsi_dln0_phy_err()
1506 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);  in dsi_fifo_status()
1521 		dsi_write(msm_host, REG_DSI_STATUS0, status);  in dsi_status()
1534 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);  in dsi_clk_status()
1565 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);  in dsi_host_irq()
2048 	dsi_write(msm_host, REG_DSI_CTRL,  in msm_dsi_host_xfer_prepare()
2064 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);  in msm_dsi_host_xfer_restore()
2132 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,  in msm_dsi_host_cmd_rx()
2135 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);  in msm_dsi_host_cmd_rx()
2223 	dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);  in msm_dsi_host_cmd_xfer_commit()
2224 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);  in msm_dsi_host_cmd_xfer_commit()
2225 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);  in msm_dsi_host_cmd_xfer_commit()
2287 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);  in msm_dsi_host_reset_phy()
2291 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);  in msm_dsi_host_reset_phy()