113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)  in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)  in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)  in DSI_6G_HW_VERSION_STEP()
180 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)  in DSI_VID_CFG0_VIRT_CHANNEL()
186 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)  in DSI_VID_CFG0_DST_FORMAT()
192 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)  in DSI_VID_CFG0_TRAFFIC_MODE()
209 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)  in DSI_VID_CFG1_RGB_SWAP()
217 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)  in DSI_ACTIVE_H_START()
223 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)  in DSI_ACTIVE_H_END()
231 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)  in DSI_ACTIVE_V_START()
237 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)  in DSI_ACTIVE_V_END()
245 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)  in DSI_TOTAL_H_TOTAL()
251 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)  in DSI_TOTAL_V_TOTAL()
259 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)  in DSI_ACTIVE_HSYNC_START()
265 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)  in DSI_ACTIVE_HSYNC_END()
273 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)  in DSI_ACTIVE_VSYNC_HPOS_START()
279 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)  in DSI_ACTIVE_VSYNC_HPOS_END()
287 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)  in DSI_ACTIVE_VSYNC_VPOS_START()
293 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)  in DSI_ACTIVE_VSYNC_VPOS_END()
306 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)  in DSI_CMD_CFG0_DST_FORMAT()
315 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)  in DSI_CMD_CFG0_INTERLEAVE_MAX()
321 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)  in DSI_CMD_CFG0_RGB_SWAP()
329 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)  in DSI_CMD_CFG1_WR_MEM_START()
335 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)  in DSI_CMD_CFG1_WR_MEM_CONTINUE()
348 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)  in DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE()
354 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)  in DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL()
360 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)  in DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT()
368 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)  in DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL()
374 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)  in DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL()
382 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)  in DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE()
388 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)  in DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL()
394 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)  in DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT()
402 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)  in DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL()
408 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)  in DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL()
415 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }  in REG_DSI_RDBK()
417 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }  in REG_DSI_RDBK_DATA()
422 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)  in DSI_TRIG_CTRL_DMA_TRIGGER()
428 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)  in DSI_TRIG_CTRL_MDP_TRIGGER()
434 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)  in DSI_TRIG_CTRL_STREAM()
453 static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)  in DSI_LP_TIMER_CTRL_LP_RX_TO()
459 static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)  in DSI_LP_TIMER_CTRL_BTA_TO()
467 static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)  in DSI_HS_TIMER_CTRL_HS_TX_TO()
473 static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)  in DSI_HS_TIMER_CTRL_TIMER_RESOLUTION()
484 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)  in DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE()
490 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)  in DSI_CLKOUT_TIMING_CTRL_T_CLK_POST()
518 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)  in DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL()
565 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)  in DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2()
575 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)  in DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP()
581 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)  in DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP()
590 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)  in DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE()
596 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)  in DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL()
602 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)  in DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT()
610 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)  in DSI_RDBK_DATA_CTRL_COUNT()
619 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)  in DSI_VERSION_MAJOR()
731 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN()
733 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_0()
735 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_1()
737 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_2()
739 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x…  in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
741 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*…  in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
743 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*…  in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
760 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO()
768 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL()
776 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE()
786 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT()
794 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO()
802 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE()
810 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL()
818 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST()
826 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO()
832 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE()
840 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET()
848 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD()
960 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN()
962 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_0()
964 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_1()
966 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_2()
968 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_3()
970 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_4()
972 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0…  in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
974 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
976 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_TEST_STR_0()
978 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_TEST_STR_1()
1001 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO()
1009 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
1017 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
1028 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT()
1036 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO()
1044 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE()
1052 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL()
1060 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST()
1068 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_9_TA_GO()
1074 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE()
1082 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_10_TA_GET()
1090 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1177 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV()
1186 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET()
1192 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN()
1200 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0()
1208 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8()
1287 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN()
1289 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_0()
1291 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_1()
1293 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_2()
1295 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_3()
1297 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_4()
1299 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0…  in REG_DSI_20nm_PHY_LN_TEST_DATAPATH()
1301 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_DEBUG_SEL()
1303 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_TEST_STR_0()
1305 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_TEST_STR_1()
1328 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO()
1336 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
1344 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
1355 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT()
1363 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO()
1371 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE()
1379 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL()
1387 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST()
1395 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_9_TA_GO()
1401 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE()
1409 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_10_TA_GET()
1417 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1478 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)  in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0()
1484 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)  in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4()
1523 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)  in DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL()
1528 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN()
1530 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG0()
1533 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)  in DSI_14nm_PHY_LN_CFG0_PREPARE_DLY()
1538 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG1()
1541 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG2()
1543 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG3()
1545 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TEST_DATAPATH()
1547 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_TEST_STR()
1549 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4()
1552 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT()
1557 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5()
1560 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO()
1565 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6()
1568 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE()
1573 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_7()
1576 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL()
1581 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_8()
1584 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST()
1589 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_9()
1592 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO()
1598 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE()
1603 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_10()
1606 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET()
1611 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_11()
1614 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD()
1619 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*…  in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0()
1621 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*…  in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1()
1623 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_VREG_CNTRL()
1789 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN()
1791 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG0()
1793 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG1()
1795 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG2()
1797 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG3()
1799 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_TEST_DATAPATH()
1801 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_PIN_SWAP()
1803 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL()
1805 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL()
1807 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL()
1809 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL()
1811 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_LPRX_CTRL()
1813 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_TX_DCTRL()
1991 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN()
1993 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_CFG0()
1995 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_CFG1()
1997 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_CFG2()
1999 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0;…  in REG_DSI_7nm_PHY_LN_TEST_DATAPATH()
2001 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_PIN_SWAP()
2003 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_LPRX_CTRL()
2005 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_TX_DCTRL()