475 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE_0_DST_OFF()  argument
477 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;  in CP_LOAD_STATE_0_DST_OFF()
481 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)  in CP_LOAD_STATE_0_STATE_SRC()  argument
483 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;  in CP_LOAD_STATE_0_STATE_SRC()
487 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)  in CP_LOAD_STATE_0_STATE_BLOCK()  argument
489 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE_0_STATE_BLOCK()
493 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE_0_NUM_UNIT()  argument
495 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;  in CP_LOAD_STATE_0_NUM_UNIT()
501 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)  in CP_LOAD_STATE_1_STATE_TYPE()  argument
503 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;  in CP_LOAD_STATE_1_STATE_TYPE()
507 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE_1_EXT_SRC_ADDR()  argument
509 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE_1_EXT_SRC_ADDR()
515 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE4_0_DST_OFF()  argument
517 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;  in CP_LOAD_STATE4_0_DST_OFF()
521 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)  in CP_LOAD_STATE4_0_STATE_SRC()  argument
523 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;  in CP_LOAD_STATE4_0_STATE_SRC()
527 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)  in CP_LOAD_STATE4_0_STATE_BLOCK()  argument
529 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE4_0_STATE_BLOCK()
533 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE4_0_NUM_UNIT()  argument
535 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;  in CP_LOAD_STATE4_0_NUM_UNIT()
541 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)  in CP_LOAD_STATE4_1_STATE_TYPE()  argument
543 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;  in CP_LOAD_STATE4_1_STATE_TYPE()
547 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()  argument
549 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()
555 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()  argument
557 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()
563 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE6_0_DST_OFF()  argument
565 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;  in CP_LOAD_STATE6_0_DST_OFF()
569 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)  in CP_LOAD_STATE6_0_STATE_TYPE()  argument
571 	return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;  in CP_LOAD_STATE6_0_STATE_TYPE()
575 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)  in CP_LOAD_STATE6_0_STATE_SRC()  argument
577 	return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;  in CP_LOAD_STATE6_0_STATE_SRC()
581 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)  in CP_LOAD_STATE6_0_STATE_BLOCK()  argument
583 	return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE6_0_STATE_BLOCK()
587 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE6_0_NUM_UNIT()  argument
589 	return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;  in CP_LOAD_STATE6_0_NUM_UNIT()
595 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()  argument
597 	return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()
603 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()  argument
605 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()
613 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_0_VIZ_QUERY()  argument
615 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_0_VIZ_QUERY()
621 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_1_PRIM_TYPE()  argument
623 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_1_PRIM_TYPE()
627 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_1_SOURCE_SELECT()  argument
629 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_1_SOURCE_SELECT()
633 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_1_VIS_CULL()  argument
635 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;  in CP_DRAW_INDX_1_VIS_CULL()
639 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_1_INDEX_SIZE()  argument
641 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_1_INDEX_SIZE()
648 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_1_NUM_INSTANCES()  argument
650 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_1_NUM_INSTANCES()
656 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_NUM_INDICES()  argument
658 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_NUM_INDICES()
664 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_3_INDX_BASE()  argument
666 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;  in CP_DRAW_INDX_3_INDX_BASE()
672 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_4_INDX_SIZE()  argument
674 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;  in CP_DRAW_INDX_4_INDX_SIZE()
680 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_2_0_VIZ_QUERY()  argument
682 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_2_0_VIZ_QUERY()
688 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_2_1_PRIM_TYPE()  argument
690 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_2_1_PRIM_TYPE()
694 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_2_1_SOURCE_SELECT()  argument
696 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_2_1_SOURCE_SELECT()
700 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_2_1_VIS_CULL()  argument
702 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;  in CP_DRAW_INDX_2_1_VIS_CULL()
706 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_2_1_INDEX_SIZE()  argument
708 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_2_1_INDEX_SIZE()
715 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_2_1_NUM_INSTANCES()  argument
717 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_2_1_NUM_INSTANCES()
723 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_2_NUM_INDICES()  argument
725 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_2_NUM_INDICES()
731 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()  argument
733 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
737 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()  argument
739 …return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT…  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
743 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()  argument
745 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()
749 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()  argument
751 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
755 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()  argument
757 	return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()
765 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()  argument
767 …return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES…  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()
773 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()  argument
775 …return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MA…  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()
781 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)  in CP_DRAW_INDX_OFFSET_3_FIRST_INDX()  argument
783 	return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;  in CP_DRAW_INDX_OFFSET_3_FIRST_INDX()
790 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO()  argument
792 …return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__…  in CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO()
798 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI()  argument
800 …return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__…  in CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI()
808 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_6_MAX_INDICES()  argument
810 …return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MA…  in CP_DRAW_INDX_OFFSET_6_MAX_INDICES()
816 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()  argument
818 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()
824 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()  argument
826 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()
832 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()  argument
834 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MA…  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()
838 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()  argument
840 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SE…  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()
844 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()  argument
846 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()
850 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()  argument
852 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__…  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()
856 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()  argument
858 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__…  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()
867 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()  argument
869 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()
876 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO()  argument
878 …return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO…  in A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO()
884 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()  argument
886 …return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI…  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()
894 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()  argument
896 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRI…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()
900 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()  argument
902 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0…  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()
906 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()  argument
908 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_…  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()
912 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()  argument
914 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_IN…  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()
918 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()  argument
920 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PA…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()
929 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()  argument
931 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()
937 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()  argument
939 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()
945 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()  argument
947 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDI…  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()
954 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()  argument
956 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_…  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()
962 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()  argument
964 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_…  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()
972 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()  argument
974 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_M…  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()
980 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()  argument
982 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_I…  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()
988 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()  argument
990 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_I…  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()
998 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()  argument
1000 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_P…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()
1004 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()  argument
1006 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()
1010 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()  argument
1012 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VI…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()
1016 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()  argument
1018 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()
1022 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()  argument
1024 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()
1032 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()  argument
1034 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCO…  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()
1038 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF()  argument
1040 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST…  in A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF()
1046 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)  in A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT()  argument
1048 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_…  in A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT()
1056 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)  in A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0()  argument
1058 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PAR…  in A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0()
1066 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)  in A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE()  argument
1068 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRI…  in A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE()
1076 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)  in CP_SET_DRAW_STATE__0_COUNT()  argument
1078 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;  in CP_SET_DRAW_STATE__0_COUNT()
1089 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)  in CP_SET_DRAW_STATE__0_GROUP_ID()  argument
1091 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;  in CP_SET_DRAW_STATE__0_GROUP_ID()
1097 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)  in CP_SET_DRAW_STATE__1_ADDR_LO()  argument
1099 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;  in CP_SET_DRAW_STATE__1_ADDR_LO()
1105 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)  in CP_SET_DRAW_STATE__2_ADDR_HI()  argument
1107 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;  in CP_SET_DRAW_STATE__2_ADDR_HI()
1115 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)  in CP_SET_BIN_1_X1()  argument
1117 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;  in CP_SET_BIN_1_X1()
1121 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)  in CP_SET_BIN_1_Y1()  argument
1123 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;  in CP_SET_BIN_1_Y1()
1129 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)  in CP_SET_BIN_2_X2()  argument
1131 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;  in CP_SET_BIN_2_X2()
1135 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)  in CP_SET_BIN_2_Y2()  argument
1137 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;  in CP_SET_BIN_2_Y2()
1143 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()  argument
1145 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()
1151 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()  argument
1153 …return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__…  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()
1159 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_SIZE()  argument
1161 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;  in CP_SET_BIN_DATA5_0_VSC_SIZE()
1165 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_N()  argument
1167 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_0_VSC_N()
1173 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()  argument
1175 …return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO…  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()
1181 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()  argument
1183 …return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI…  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()
1189 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()  argument
1191 …return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()
1197 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()  argument
1199 …return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()
1205 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)  in CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO()  argument
1207 …return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO…  in CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO()
1213 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)  in CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI()  argument
1215 …return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI…  in CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI()
1221 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE()  argument
1223 …return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__…  in CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE()
1227 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_0_VSC_N()  argument
1229 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_OFFSET_0_VSC_N()
1235 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET()  argument
1237 …return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN…  in CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET()
1243 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET()  argument
1245 …return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN…  in CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET()
1251 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET()  argument
1253 …return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BI…  in CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET()
1259 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)  in CP_REG_RMW_0_DST_REG()  argument
1261 	return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;  in CP_REG_RMW_0_DST_REG()
1265 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)  in CP_REG_RMW_0_ROTATE()  argument
1267 	return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;  in CP_REG_RMW_0_ROTATE()
1276 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)  in CP_REG_RMW_1_SRC0()  argument
1278 	return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;  in CP_REG_RMW_1_SRC0()
1284 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)  in CP_REG_RMW_2_SRC1()  argument
1286 	return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;  in CP_REG_RMW_2_SRC1()
1292 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_0_REG()  argument
1294 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;  in CP_REG_TO_MEM_0_REG()
1298 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_0_CNT()  argument
1300 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_0_CNT()
1308 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_1_DEST()  argument
1310 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_1_DEST()
1316 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_2_DEST_HI()  argument
1318 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;  in CP_REG_TO_MEM_2_DEST_HI()
1324 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_0_REG()  argument
1326 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;  in CP_REG_TO_MEM_OFFSET_REG_0_REG()
1330 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_0_CNT()  argument
1332 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;  in CP_REG_TO_MEM_OFFSET_REG_0_CNT()
1340 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_1_DEST()  argument
1342 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;  in CP_REG_TO_MEM_OFFSET_REG_1_DEST()
1348 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI()  argument
1350 …return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__…  in CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI()
1356 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0()  argument
1358 …return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__…  in CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0()
1365 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_0_REG()  argument
1367 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_0_REG()
1371 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_0_CNT()  argument
1373 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_0_CNT()
1381 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_1_DEST()  argument
1383 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_1_DEST()
1389 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI()  argument
1391 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__…  in CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI()
1397 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO()  argument
1399 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_…  in CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO()
1405 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI()  argument
1407 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_…  in CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI()
1413 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)  in CP_MEM_TO_REG_0_REG()  argument
1415 	return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;  in CP_MEM_TO_REG_0_REG()
1419 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)  in CP_MEM_TO_REG_0_CNT()  argument
1421 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;  in CP_MEM_TO_REG_0_CNT()
1429 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)  in CP_MEM_TO_REG_1_SRC()  argument
1431 	return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;  in CP_MEM_TO_REG_1_SRC()
1437 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)  in CP_MEM_TO_REG_2_SRC_HI()  argument
1439 	return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;  in CP_MEM_TO_REG_2_SRC_HI()
1453 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)  in CP_MEMCPY_0_DWORDS()  argument
1455 	return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;  in CP_MEMCPY_0_DWORDS()
1461 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)  in CP_MEMCPY_1_SRC_LO()  argument
1463 	return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;  in CP_MEMCPY_1_SRC_LO()
1469 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)  in CP_MEMCPY_2_SRC_HI()  argument
1471 	return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;  in CP_MEMCPY_2_SRC_HI()
1477 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)  in CP_MEMCPY_3_DST_LO()  argument
1479 	return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;  in CP_MEMCPY_3_DST_LO()
1485 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)  in CP_MEMCPY_4_DST_HI()  argument
1487 	return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;  in CP_MEMCPY_4_DST_HI()
1493 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)  in CP_REG_TO_SCRATCH_0_REG()  argument
1495 	return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;  in CP_REG_TO_SCRATCH_0_REG()
1499 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)  in CP_REG_TO_SCRATCH_0_SCRATCH()  argument
1501 	return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;  in CP_REG_TO_SCRATCH_0_SCRATCH()
1505 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)  in CP_REG_TO_SCRATCH_0_CNT()  argument
1507 	return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;  in CP_REG_TO_SCRATCH_0_CNT()
1513 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)  in CP_SCRATCH_TO_REG_0_REG()  argument
1515 	return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;  in CP_SCRATCH_TO_REG_0_REG()
1520 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)  in CP_SCRATCH_TO_REG_0_SCRATCH()  argument
1522 	return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;  in CP_SCRATCH_TO_REG_0_SCRATCH()
1526 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)  in CP_SCRATCH_TO_REG_0_CNT()  argument
1528 	return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;  in CP_SCRATCH_TO_REG_0_CNT()
1534 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)  in CP_SCRATCH_WRITE_0_SCRATCH()  argument
1536 	return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;  in CP_SCRATCH_WRITE_0_SCRATCH()
1542 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)  in CP_MEM_WRITE_0_ADDR_LO()  argument
1544 	return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;  in CP_MEM_WRITE_0_ADDR_LO()
1550 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)  in CP_MEM_WRITE_1_ADDR_HI()  argument
1552 	return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;  in CP_MEM_WRITE_1_ADDR_HI()
1558 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE_0_FUNCTION()  argument
1560 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;  in CP_COND_WRITE_0_FUNCTION()
1568 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)  in CP_COND_WRITE_1_POLL_ADDR()  argument
1570 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;  in CP_COND_WRITE_1_POLL_ADDR()
1576 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)  in CP_COND_WRITE_2_REF()  argument
1578 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;  in CP_COND_WRITE_2_REF()
1584 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)  in CP_COND_WRITE_3_MASK()  argument
1586 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;  in CP_COND_WRITE_3_MASK()
1592 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)  in CP_COND_WRITE_4_WRITE_ADDR()  argument
1594 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;  in CP_COND_WRITE_4_WRITE_ADDR()
1600 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)  in CP_COND_WRITE_5_WRITE_DATA()  argument
1602 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;  in CP_COND_WRITE_5_WRITE_DATA()
1608 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE5_0_FUNCTION()  argument
1610 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;  in CP_COND_WRITE5_0_FUNCTION()
1620 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_1_POLL_ADDR_LO()  argument
1622 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;  in CP_COND_WRITE5_1_POLL_ADDR_LO()
1628 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_2_POLL_ADDR_HI()  argument
1630 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;  in CP_COND_WRITE5_2_POLL_ADDR_HI()
1636 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)  in CP_COND_WRITE5_3_REF()  argument
1638 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;  in CP_COND_WRITE5_3_REF()
1644 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)  in CP_COND_WRITE5_4_MASK()  argument
1646 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;  in CP_COND_WRITE5_4_MASK()
1652 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_5_WRITE_ADDR_LO()  argument
1654 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;  in CP_COND_WRITE5_5_WRITE_ADDR_LO()
1660 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_6_WRITE_ADDR_HI()  argument
1662 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;  in CP_COND_WRITE5_6_WRITE_ADDR_HI()
1668 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)  in CP_COND_WRITE5_7_WRITE_DATA()  argument
1670 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;  in CP_COND_WRITE5_7_WRITE_DATA()
1676 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)  in CP_WAIT_MEM_GTE_0_RESERVED()  argument
1678 	return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;  in CP_WAIT_MEM_GTE_0_RESERVED()
1684 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)  in CP_WAIT_MEM_GTE_1_POLL_ADDR_LO()  argument
1686 	return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;  in CP_WAIT_MEM_GTE_1_POLL_ADDR_LO()
1692 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)  in CP_WAIT_MEM_GTE_2_POLL_ADDR_HI()  argument
1694 	return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;  in CP_WAIT_MEM_GTE_2_POLL_ADDR_HI()
1700 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)  in CP_WAIT_MEM_GTE_3_REF()  argument
1702 	return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;  in CP_WAIT_MEM_GTE_3_REF()
1708 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)  in CP_WAIT_REG_MEM_0_FUNCTION()  argument
1710 	return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;  in CP_WAIT_REG_MEM_0_FUNCTION()
1720 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)  in CP_WAIT_REG_MEM_1_POLL_ADDR_LO()  argument
1722 	return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;  in CP_WAIT_REG_MEM_1_POLL_ADDR_LO()
1728 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)  in CP_WAIT_REG_MEM_2_POLL_ADDR_HI()  argument
1730 	return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;  in CP_WAIT_REG_MEM_2_POLL_ADDR_HI()
1736 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)  in CP_WAIT_REG_MEM_3_REF()  argument
1738 	return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;  in CP_WAIT_REG_MEM_3_REF()
1744 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)  in CP_WAIT_REG_MEM_4_MASK()  argument
1746 	return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;  in CP_WAIT_REG_MEM_4_MASK()
1752 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)  in CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES()  argument
1754 …return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES…  in CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES()
1760 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)  in CP_WAIT_TWO_REGS_0_REG0()  argument
1762 	return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;  in CP_WAIT_TWO_REGS_0_REG0()
1768 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)  in CP_WAIT_TWO_REGS_1_REG1()  argument
1770 	return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;  in CP_WAIT_TWO_REGS_1_REG1()
1776 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)  in CP_WAIT_TWO_REGS_2_REF()  argument
1778 	return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;  in CP_WAIT_TWO_REGS_2_REF()
1786 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)  in CP_DISPATCH_COMPUTE_1_X()  argument
1788 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;  in CP_DISPATCH_COMPUTE_1_X()
1794 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)  in CP_DISPATCH_COMPUTE_2_Y()  argument
1796 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;  in CP_DISPATCH_COMPUTE_2_Y()
1802 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)  in CP_DISPATCH_COMPUTE_3_Z()  argument
1804 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;  in CP_DISPATCH_COMPUTE_3_Z()
1810 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)  in CP_SET_RENDER_MODE_0_MODE()  argument
1812 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;  in CP_SET_RENDER_MODE_0_MODE()
1818 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)  in CP_SET_RENDER_MODE_1_ADDR_0_LO()  argument
1820 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;  in CP_SET_RENDER_MODE_1_ADDR_0_LO()
1826 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)  in CP_SET_RENDER_MODE_2_ADDR_0_HI()  argument
1828 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;  in CP_SET_RENDER_MODE_2_ADDR_0_HI()
1840 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()  argument
1842 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()
1848 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)  in CP_SET_RENDER_MODE_6_ADDR_1_LO()  argument
1850 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;  in CP_SET_RENDER_MODE_6_ADDR_1_LO()
1856 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)  in CP_SET_RENDER_MODE_7_ADDR_1_HI()  argument
1858 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;  in CP_SET_RENDER_MODE_7_ADDR_1_HI()
1864 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()  argument
1866 …return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MA…  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()
1872 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()  argument
1874 …return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MA…  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()
1882 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()  argument
1884 …return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__…  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()
1892 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()  argument
1894 …return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MA…  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()
1900 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()  argument
1902 …return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MA…  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()
1912 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()  argument
1914 …return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MA…  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()
1920 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()  argument
1922 …return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MA…  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()
1928 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)  in CP_EVENT_WRITE_0_EVENT()  argument
1930 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;  in CP_EVENT_WRITE_0_EVENT()
1938 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)  in CP_EVENT_WRITE_1_ADDR_0_LO()  argument
1940 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;  in CP_EVENT_WRITE_1_ADDR_0_LO()
1946 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)  in CP_EVENT_WRITE_2_ADDR_0_HI()  argument
1948 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;  in CP_EVENT_WRITE_2_ADDR_0_HI()
1956 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)  in CP_BLIT_0_OP()  argument
1958 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;  in CP_BLIT_0_OP()
1964 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)  in CP_BLIT_1_SRC_X1()  argument
1966 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;  in CP_BLIT_1_SRC_X1()
1970 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)  in CP_BLIT_1_SRC_Y1()  argument
1972 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;  in CP_BLIT_1_SRC_Y1()
1978 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)  in CP_BLIT_2_SRC_X2()  argument
1980 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;  in CP_BLIT_2_SRC_X2()
1984 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)  in CP_BLIT_2_SRC_Y2()  argument
1986 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;  in CP_BLIT_2_SRC_Y2()
1992 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)  in CP_BLIT_3_DST_X1()  argument
1994 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;  in CP_BLIT_3_DST_X1()
1998 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)  in CP_BLIT_3_DST_Y1()  argument
2000 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;  in CP_BLIT_3_DST_Y1()
2006 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)  in CP_BLIT_4_DST_X2()  argument
2008 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;  in CP_BLIT_4_DST_X2()
2012 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)  in CP_BLIT_4_DST_Y2()  argument
2014 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;  in CP_BLIT_4_DST_Y2()
2022 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)  in CP_EXEC_CS_1_NGROUPS_X()  argument
2024 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;  in CP_EXEC_CS_1_NGROUPS_X()
2030 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)  in CP_EXEC_CS_2_NGROUPS_Y()  argument
2032 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;  in CP_EXEC_CS_2_NGROUPS_Y()
2038 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)  in CP_EXEC_CS_3_NGROUPS_Z()  argument
2040 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;  in CP_EXEC_CS_3_NGROUPS_Z()
2049 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()  argument
2051 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()
2057 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()  argument
2059 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()
2063 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()  argument
2065 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()
2069 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()  argument
2071 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()
2078 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()  argument
2080 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__…  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()
2086 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()  argument
2088 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__…  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()
2094 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()  argument
2096 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()
2100 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()  argument
2102 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()
2106 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()  argument
2108 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()
2114 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)  in A6XX_CP_SET_MARKER_0_MODE()  argument
2116 	return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;  in A6XX_CP_SET_MARKER_0_MODE()
2120 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)  in A6XX_CP_SET_MARKER_0_MARKER()  argument
2122 	return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;  in A6XX_CP_SET_MARKER_0_MARKER()
2130 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()  argument
2132 …return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_R…  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()
2138 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)  in A6XX_CP_SET_PSEUDO_REG__1_LO()  argument
2140 	return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;  in A6XX_CP_SET_PSEUDO_REG__1_LO()
2146 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)  in A6XX_CP_SET_PSEUDO_REG__2_HI()  argument
2148 	return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;  in A6XX_CP_SET_PSEUDO_REG__2_HI()
2154 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)  in A6XX_CP_REG_TEST_0_REG()  argument
2156 	return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;  in A6XX_CP_REG_TEST_0_REG()
2160 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)  in A6XX_CP_REG_TEST_0_BIT()  argument
2162 	return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;  in A6XX_CP_REG_TEST_0_BIT()
2169 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)  in CP_COND_REG_EXEC_0_REG0()  argument
2171 	return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;  in CP_COND_REG_EXEC_0_REG0()
2178 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)  in CP_COND_REG_EXEC_0_MODE()  argument
2180 	return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;  in CP_COND_REG_EXEC_0_MODE()
2186 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)  in CP_COND_REG_EXEC_1_DWORDS()  argument
2188 	return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;  in CP_COND_REG_EXEC_1_DWORDS()
2194 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)  in CP_COND_EXEC_0_ADDR0_LO()  argument
2196 	return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;  in CP_COND_EXEC_0_ADDR0_LO()
2202 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)  in CP_COND_EXEC_1_ADDR0_HI()  argument
2204 	return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;  in CP_COND_EXEC_1_ADDR0_HI()
2210 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)  in CP_COND_EXEC_2_ADDR1_LO()  argument
2212 	return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;  in CP_COND_EXEC_2_ADDR1_LO()
2218 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)  in CP_COND_EXEC_3_ADDR1_HI()  argument
2220 	return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;  in CP_COND_EXEC_3_ADDR1_HI()
2226 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)  in CP_COND_EXEC_4_REF()  argument
2228 	return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;  in CP_COND_EXEC_4_REF()
2234 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)  in CP_COND_EXEC_5_DWORDS()  argument
2236 	return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;  in CP_COND_EXEC_5_DWORDS()
2242 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)  in CP_SET_CTXSWITCH_IB_0_ADDR_LO()  argument
2244 	return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;  in CP_SET_CTXSWITCH_IB_0_ADDR_LO()
2250 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)  in CP_SET_CTXSWITCH_IB_1_ADDR_HI()  argument
2252 	return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;  in CP_SET_CTXSWITCH_IB_1_ADDR_HI()
2258 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)  in CP_SET_CTXSWITCH_IB_2_DWORDS()  argument
2260 	return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;  in CP_SET_CTXSWITCH_IB_2_DWORDS()
2264 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)  in CP_SET_CTXSWITCH_IB_2_TYPE()  argument
2266 	return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;  in CP_SET_CTXSWITCH_IB_2_TYPE()
2272 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)  in CP_REG_WRITE_0_TRACKER()  argument
2274 	return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;  in CP_REG_WRITE_0_TRACKER()
2280 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)  in CP_SMMU_TABLE_UPDATE_0_TTBR0_LO()  argument
2282 	return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;  in CP_SMMU_TABLE_UPDATE_0_TTBR0_LO()
2288 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)  in CP_SMMU_TABLE_UPDATE_1_TTBR0_HI()  argument
2290 	return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;  in CP_SMMU_TABLE_UPDATE_1_TTBR0_HI()
2294 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)  in CP_SMMU_TABLE_UPDATE_1_ASID()  argument
2296 	return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;  in CP_SMMU_TABLE_UPDATE_1_ASID()
2302 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)  in CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR()  argument
2304 …return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MA…  in CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR()
2310 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)  in CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK()  argument
2312 …return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__…  in CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK()