25 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &  in _a6xx_check_idle()
29 	return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &  in _a6xx_check_idle()
42 			gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_idle()
43 			gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),  in a6xx_idle()
44 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_idle()
45 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));  in a6xx_idle()
444 	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);  in a6xx_set_hwcg()
874 			gpu_read(gpu, REG_A6XX_RBBM_STATUS));  in a6xx_dump()
891 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));  in a6xx_recover()
914 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),  in a6xx_fault_handler()
915 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),  in a6xx_fault_handler()
916 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),  in a6xx_fault_handler()
917 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));  in a6xx_fault_handler()
924 	u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);  in a6xx_cp_hw_err_irq()
930 		val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);  in a6xx_cp_hw_err_irq()
942 			gpu_read(gpu, REG_A6XX_CP_HW_FAULT));  in a6xx_cp_hw_err_irq()
945 		u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);  in a6xx_cp_hw_err_irq()
981 		gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_fault_detect_irq()
982 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_fault_detect_irq()
983 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a6xx_fault_detect_irq()
985 		gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_fault_detect_irq()
987 		gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));  in a6xx_fault_detect_irq()
997 	u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);  in a6xx_irq()
1150 	return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);  in a6xx_get_rptr()