478 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)  in pdc_write()  function
537 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);  in a6xx_gmu_rpmh_init()
538 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);  in a6xx_gmu_rpmh_init()
539 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);  in a6xx_gmu_rpmh_init()
540 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);  in a6xx_gmu_rpmh_init()
541 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);  in a6xx_gmu_rpmh_init()
544 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);  in a6xx_gmu_rpmh_init()
545 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
546 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);  in a6xx_gmu_rpmh_init()
547 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
548 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
549 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);  in a6xx_gmu_rpmh_init()
550 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
551 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
552 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);  in a6xx_gmu_rpmh_init()
554 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
555 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);  in a6xx_gmu_rpmh_init()
556 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);  in a6xx_gmu_rpmh_init()
558 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);  in a6xx_gmu_rpmh_init()
559 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
560 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);  in a6xx_gmu_rpmh_init()
561 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
562 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
563 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);  in a6xx_gmu_rpmh_init()
565 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
566 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
568 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);  in a6xx_gmu_rpmh_init()
570 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);  in a6xx_gmu_rpmh_init()
571 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
572 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);  in a6xx_gmu_rpmh_init()
573 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);  in a6xx_gmu_rpmh_init()
576 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
577 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);  in a6xx_gmu_rpmh_init()