851 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i)));  in a5xx_recover()
858 	gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD);  in a5xx_recover()
898 	if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY)  in _a5xx_check_idle()
905 	return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) &  in _a5xx_check_idle()
926 			gpu_read(gpu, REG_A5XX_RBBM_STATUS),  in a5xx_idle()
927 			gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS),  in a5xx_idle()
928 			gpu_read(gpu, REG_A5XX_CP_RB_RPTR),  in a5xx_idle()
929 			gpu_read(gpu, REG_A5XX_CP_RB_WPTR));  in a5xx_idle()
941 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)),  in a5xx_fault_handler()
942 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)),  in a5xx_fault_handler()
943 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),  in a5xx_fault_handler()
944 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));  in a5xx_fault_handler()
951 	u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS);  in a5xx_cp_err_irq()
963 		gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA);  in a5xx_cp_err_irq()
964 		val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA);  in a5xx_cp_err_irq()
972 			gpu_read(gpu, REG_A5XX_CP_HW_FAULT));  in a5xx_cp_err_irq()
978 		u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS);  in a5xx_cp_err_irq()
987 		u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT);  in a5xx_cp_err_irq()
1003 		u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS);  in a5xx_rbbm_err_irq()
1024 			gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS));  in a5xx_rbbm_err_irq()
1028 			gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS));  in a5xx_rbbm_err_irq()
1032 			gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS));  in a5xx_rbbm_err_irq()
1043 	uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI);  in a5xx_uche_err_irq()
1045 	addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO);  in a5xx_uche_err_irq()
1064 		gpu_read(gpu, REG_A5XX_RBBM_STATUS),  in a5xx_fault_detect_irq()
1065 		gpu_read(gpu, REG_A5XX_CP_RB_RPTR),  in a5xx_fault_detect_irq()
1066 		gpu_read(gpu, REG_A5XX_CP_RB_WPTR),  in a5xx_fault_detect_irq()
1068 		gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ),  in a5xx_fault_detect_irq()
1070 		gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));  in a5xx_fault_detect_irq()
1088 	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);  in a5xx_irq()
1158 		gpu_read(gpu, REG_A5XX_RBBM_STATUS));  in a5xx_dump()
1192 			gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS));  in a5xx_pm_resume()
1218 	spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) &  in a5xx_pm_suspend()
1382 	a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);  in a5xx_gpu_state_get()
1496 	return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR);  in a5xx_get_rptr()