35 		OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));  in a5xx_flush()
36 		OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));  in a5xx_flush()
95 				OUT_RING(ring, ptr[i]);  in a5xx_submit_in_rb()
131 	OUT_RING(ring, 0x02);  in a5xx_submit()
135 	OUT_RING(ring, 0);  in a5xx_submit()
139 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
140 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
144 	OUT_RING(ring, 1);  in a5xx_submit()
148 	OUT_RING(ring, 0x02);  in a5xx_submit()
152 	OUT_RING(ring, 0x02);  in a5xx_submit()
165 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a5xx_submit()
166 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a5xx_submit()
167 			OUT_RING(ring, submit->cmd[i].size);  in a5xx_submit()
179 	OUT_RING(ring, 0);  in a5xx_submit()
180 	OUT_RING(ring, 0);  in a5xx_submit()
181 	OUT_RING(ring, 0);  in a5xx_submit()
182 	OUT_RING(ring, 0);  in a5xx_submit()
183 	OUT_RING(ring, 0);  in a5xx_submit()
187 	OUT_RING(ring, 0x01);  in a5xx_submit()
191 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
198 	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |  in a5xx_submit()
200 	OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));  in a5xx_submit()
201 	OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));  in a5xx_submit()
202 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
211 	OUT_RING(ring, 0x00);  in a5xx_submit()
212 	OUT_RING(ring, 0x00);  in a5xx_submit()
214 	OUT_RING(ring, 0x01);  in a5xx_submit()
216 	OUT_RING(ring, 0x01);  in a5xx_submit()
348 	OUT_RING(ring, 0x0000002F);  in a5xx_me_init()
351 	OUT_RING(ring, 0x00000003);  in a5xx_me_init()
354 	OUT_RING(ring, 0x20000000);  in a5xx_me_init()
357 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
358 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
366 		OUT_RING(ring, 0x0000000B);  in a5xx_me_init()
369 		OUT_RING(ring, 0x00000001);  in a5xx_me_init()
372 		OUT_RING(ring, 0x00000000);  in a5xx_me_init()
375 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
376 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
393 	OUT_RING(ring, 0);  in a5xx_preempt_start()
397 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id]));  in a5xx_preempt_start()
398 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id]));  in a5xx_preempt_start()
402 	OUT_RING(ring, 1);  in a5xx_preempt_start()
405 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
408 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
411 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
415 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
416 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
417 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
418 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
800 		OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT));  in a5xx_hw_init()
818 		OUT_RING(gpu->rb[0], 0x00000000);  in a5xx_hw_init()