31 	for (i = 0; i < submit->nr_cmds; i++) {  in a4xx_submit()
62 	OUT_RING(ring, 0x00000000);  in a4xx_submit()
81 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
82 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202);  in a4xx_enable_hwcg()
83 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
84 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222);  in a4xx_enable_hwcg()
85 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
86 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7);  in a4xx_enable_hwcg()
87 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
88 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111);  in a4xx_enable_hwcg()
89 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
90 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222);  in a4xx_enable_hwcg()
91 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
92 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222);  in a4xx_enable_hwcg()
93 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
94 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104);  in a4xx_enable_hwcg()
95 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
96 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081);  in a4xx_enable_hwcg()
97 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222);  in a4xx_enable_hwcg()
98 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222);  in a4xx_enable_hwcg()
99 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL3_UCHE, 0x00000000);  in a4xx_enable_hwcg()
100 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL4_UCHE, 0x00000000);  in a4xx_enable_hwcg()
101 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_UCHE, 0x00004444);  in a4xx_enable_hwcg()
102 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_UCHE, 0x00001112);  in a4xx_enable_hwcg()
103 	for (i = 0; i < 4; i++)  in a4xx_enable_hwcg()
104 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_RB(i), 0x22222222);  in a4xx_enable_hwcg()
107 	for (i = 0; i < 4; i++) {  in a4xx_enable_hwcg()
110 					0x00002020);  in a4xx_enable_hwcg()
113 					0x00022020);  in a4xx_enable_hwcg()
119 		for (i = 0; i < 4; i++) {  in a4xx_enable_hwcg()
121 					0x00000922);  in a4xx_enable_hwcg()
124 		for (i = 0; i < 4; i++) {  in a4xx_enable_hwcg()
126 					0x00000000);  in a4xx_enable_hwcg()
129 		for (i = 0; i < 4; i++) {  in a4xx_enable_hwcg()
131 					0x00000001);  in a4xx_enable_hwcg()
135 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);  in a4xx_enable_hwcg()
136 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104);  in a4xx_enable_hwcg()
137 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_GPC, 0x00022222);  in a4xx_enable_hwcg()
138 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM, 0x00000022);  in a4xx_enable_hwcg()
139 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM, 0x0000010F);  in a4xx_enable_hwcg()
140 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM, 0x00000022);  in a4xx_enable_hwcg()
141 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM, 0x00222222);  in a4xx_enable_hwcg()
142 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00004104);  in a4xx_enable_hwcg()
143 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222);  in a4xx_enable_hwcg()
144 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000);  in a4xx_enable_hwcg()
145 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000);  in a4xx_enable_hwcg()
146 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);  in a4xx_enable_hwcg()
150 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);  in a4xx_enable_hwcg()
152 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);  in a4xx_enable_hwcg()
153 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0);  in a4xx_enable_hwcg()
159 	struct msm_ringbuffer *ring = gpu->rb[0];  in a4xx_me_init()
162 	OUT_RING(ring, 0x000003f7);  in a4xx_me_init()
163 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
164 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
165 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
166 	OUT_RING(ring, 0x00000080);  in a4xx_me_init()
167 	OUT_RING(ring, 0x00000100);  in a4xx_me_init()
168 	OUT_RING(ring, 0x00000180);  in a4xx_me_init()
169 	OUT_RING(ring, 0x00006600);  in a4xx_me_init()
170 	OUT_RING(ring, 0x00000150);  in a4xx_me_init()
171 	OUT_RING(ring, 0x0000014e);  in a4xx_me_init()
172 	OUT_RING(ring, 0x00000154);  in a4xx_me_init()
173 	OUT_RING(ring, 0x00000001);  in a4xx_me_init()
174 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
175 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
176 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
177 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
178 	OUT_RING(ring, 0x00000000);  in a4xx_me_init()
192 		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);  in a4xx_hw_init()
194 		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);  in a4xx_hw_init()
195 		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);  in a4xx_hw_init()
196 		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);  in a4xx_hw_init()
197 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);  in a4xx_hw_init()
198 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);  in a4xx_hw_init()
199 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);  in a4xx_hw_init()
200 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);  in a4xx_hw_init()
201 		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);  in a4xx_hw_init()
203 		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);  in a4xx_hw_init()
204 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);  in a4xx_hw_init()
205 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);  in a4xx_hw_init()
206 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);  in a4xx_hw_init()
207 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);  in a4xx_hw_init()
208 		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);  in a4xx_hw_init()
214 	gpu_write(gpu, REG_A4XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);  in a4xx_hw_init()
217 	gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10);  in a4xx_hw_init()
218 	gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);  in a4xx_hw_init()
221 		gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30);  in a4xx_hw_init()
225 	gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);  in a4xx_hw_init()
228 	gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL1, 0xa6ffffff);  in a4xx_hw_init()
231 	gpu_write(gpu, REG_A4XX_RBBM_RBBM_CTL, 0x00000030);  in a4xx_hw_init()
238 			(1 << 30) | 0xFFFF);  in a4xx_hw_init()
244 	gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01);  in a4xx_hw_init()
252 		gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07);  in a4xx_hw_init()
255 	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000);  in a4xx_hw_init()
256 	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000);  in a4xx_hw_init()
259 			(adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));  in a4xx_hw_init()
265 			0x00000441);  in a4xx_hw_init()
267 			0x00000441);  in a4xx_hw_init()
285 	gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007);  in a4xx_hw_init()
288 	gpu_write(gpu, REG_A4XX_CP_PROTECT(0), 0x62000010);  in a4xx_hw_init()
289 	gpu_write(gpu, REG_A4XX_CP_PROTECT(1), 0x63000020);  in a4xx_hw_init()
290 	gpu_write(gpu, REG_A4XX_CP_PROTECT(2), 0x64000040);  in a4xx_hw_init()
291 	gpu_write(gpu, REG_A4XX_CP_PROTECT(3), 0x65000080);  in a4xx_hw_init()
292 	gpu_write(gpu, REG_A4XX_CP_PROTECT(4), 0x66000100);  in a4xx_hw_init()
293 	gpu_write(gpu, REG_A4XX_CP_PROTECT(5), 0x64000200);  in a4xx_hw_init()
296 	gpu_write(gpu, REG_A4XX_CP_PROTECT(6), 0x67000800);  in a4xx_hw_init()
297 	gpu_write(gpu, REG_A4XX_CP_PROTECT(7), 0x64001600);  in a4xx_hw_init()
301 	gpu_write(gpu, REG_A4XX_CP_PROTECT(8), 0x60003300);  in a4xx_hw_init()
304 	gpu_write(gpu, REG_A4XX_CP_PROTECT(9), 0x60003800);  in a4xx_hw_init()
307 	gpu_write(gpu, REG_A4XX_CP_PROTECT(10), 0x61003980);  in a4xx_hw_init()
310 	gpu_write(gpu, REG_A4XX_CP_PROTECT(11), 0x6e010000);  in a4xx_hw_init()
326 	gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));  in a4xx_hw_init()
331 	DBG("loading PM4 ucode version: %u", ptr[0]);  in a4xx_hw_init()
332 	gpu_write(gpu, REG_A4XX_CP_ME_RAM_WADDR, 0);  in a4xx_hw_init()
339 	DBG("loading PFP ucode version: %u", ptr[0]);  in a4xx_hw_init()
341 	gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_ADDR, 0);  in a4xx_hw_init()
346 	gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0);  in a4xx_hw_init()
348 	return a4xx_me_init(gpu) ? 0 : -EINVAL;  in a4xx_hw_init()
357 	for (i = 0; i < 8; i++) {  in a4xx_recover()
368 	gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 0);  in a4xx_recover()
389 	if (!adreno_idle(gpu, gpu->rb[0]))  in a4xx_idle()
414 			(reg & 0xFFFFF) >> 2);  in a4xx_irq()
426 	0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026,
427 	0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066,
428 	0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF,
430 	0x0200, 0x0233, 0x0240, 0x0250, 0x04C0, 0x04DD, 0x0500, 0x050B,
431 	0x0578, 0x058F,
433 	0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51,
435 	0x0C80, 0x0C81, 0x0C88, 0x0C8F,
437 	0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2,
439 	0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23,
441 	0x0E40, 0x0E4A,
443 	0x0E60, 0x0E61, 0x0E63, 0x0E68,
445 	0x0E80, 0x0E84, 0x0E88, 0x0E95,
447 	0x1000, 0x1000, 0x1002, 0x1002, 0x1004, 0x1004, 0x1008, 0x100A,
448 	0x100C, 0x100D, 0x100F, 0x1010, 0x1012, 0x1016, 0x1024, 0x1024,
449 	0x1027, 0x1027, 0x1100, 0x1100, 0x1102, 0x1102, 0x1104, 0x1104,
450 	0x1110, 0x1110, 0x1112, 0x1116, 0x1124, 0x1124, 0x1300, 0x1300,
451 	0x1380, 0x1380,
452 	/* GRAS CTX 0 */
453 	0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E,
454 	/* PC CTX 0 */
455 	0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7,
456 	/* VFD CTX 0 */
457 	0x2200, 0x2204, 0x2208, 0x22A9,
459 	0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E,
461 	0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7,
463 	0x2600, 0x2604, 0x2608, 0x26A9,
465 	0x2C00, 0x2C01, 0x2C10, 0x2C10, 0x2C12, 0x2C16, 0x2C1D, 0x2C20,
466 	0x2C28, 0x2C28, 0x2C30, 0x2C30, 0x2C32, 0x2C36, 0x2C40, 0x2C40,
467 	0x2C50, 0x2C50, 0x2C52, 0x2C56, 0x2C80, 0x2C80, 0x2C94, 0x2C95,
469 	0x3000, 0x3007, 0x300C, 0x3014, 0x3018, 0x301D, 0x3020, 0x3022,
470 	0x3024, 0x3026, 0x3028, 0x302A, 0x302C, 0x302D, 0x3030, 0x3031,
471 	0x3034, 0x3036, 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040,
472 	0x3049, 0x3049, 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068,
473 	0x306C, 0x306D, 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094,
474 	0x3098, 0x3098, 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8,
475 	0x30D0, 0x30D0, 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100,
476 	0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120,
477 	0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x330C, 0x330C,
478 	0x3310, 0x3310, 0x3400, 0x3401, 0x3410, 0x3410, 0x3412, 0x3416,
479 	0x341D, 0x3420, 0x3428, 0x3428, 0x3430, 0x3430, 0x3432, 0x3436,
480 	0x3440, 0x3440, 0x3450, 0x3450, 0x3452, 0x3456, 0x3480, 0x3480,
481 	0x3494, 0x3495, 0x4000, 0x4000, 0x4002, 0x4002, 0x4004, 0x4004,
482 	0x4008, 0x400A, 0x400C, 0x400D, 0x400F, 0x4012, 0x4014, 0x4016,
483 	0x401D, 0x401D, 0x4020, 0x4027, 0x4060, 0x4062, 0x4200, 0x4200,
484 	0x4300, 0x4300, 0x4400, 0x4400, 0x4500, 0x4500, 0x4800, 0x4802,
485 	0x480F, 0x480F, 0x4811, 0x4811, 0x4813, 0x4813, 0x4815, 0x4816,
486 	0x482B, 0x482B, 0x4857, 0x4857, 0x4883, 0x4883, 0x48AF, 0x48AF,
487 	0x48C5, 0x48C5, 0x48E5, 0x48E5, 0x4905, 0x4905, 0x4925, 0x4925,
488 	0x4945, 0x4945, 0x4950, 0x4950, 0x495B, 0x495B, 0x4980, 0x498E,
489 	0x4B00, 0x4B00, 0x4C00, 0x4C00, 0x4D00, 0x4D00, 0x4E00, 0x4E00,
490 	0x4E80, 0x4E80, 0x4F00, 0x4F00, 0x4F08, 0x4F08, 0x4F10, 0x4F10,
491 	0x4F18, 0x4F18, 0x4F20, 0x4F20, 0x4F30, 0x4F30, 0x4F60, 0x4F60,
492 	0x4F80, 0x4F81, 0x4F88, 0x4F89, 0x4FEE, 0x4FEE, 0x4FF3, 0x4FF3,
493 	0x6000, 0x6001, 0x6008, 0x600F, 0x6014, 0x6016, 0x6018, 0x601B,
494 	0x61FD, 0x61FD, 0x623C, 0x623C, 0x6380, 0x6380, 0x63A0, 0x63A0,
495 	0x63C0, 0x63C1, 0x63C8, 0x63C9, 0x63D0, 0x63D4, 0x63D6, 0x63D6,
496 	0x63EE, 0x63EE, 0x6400, 0x6401, 0x6408, 0x640F, 0x6414, 0x6416,
497 	0x6418, 0x641B, 0x65FD, 0x65FD, 0x663C, 0x663C, 0x6780, 0x6780,
498 	0x67A0, 0x67A0, 0x67C0, 0x67C1, 0x67C8, 0x67C9, 0x67D0, 0x67D4,
499 	0x67D6, 0x67D6, 0x67EE, 0x67EE, 0x6800, 0x6801, 0x6808, 0x680F,
500 	0x6814, 0x6816, 0x6818, 0x681B, 0x69FD, 0x69FD, 0x6A3C, 0x6A3C,
501 	0x6B80, 0x6B80, 0x6BA0, 0x6BA0, 0x6BC0, 0x6BC1, 0x6BC8, 0x6BC9,
502 	0x6BD0, 0x6BD4, 0x6BD6, 0x6BD6, 0x6BEE, 0x6BEE,
503 	~0 /* sentinel */
508 	0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026,
509 	0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066,
510 	0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF,
512 	0x0200, 0x0233, 0x0240, 0x0250, 0x04C0, 0x04DD, 0x0500, 0x050B,
513 	0x0578, 0x058F,
515 	0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51,
517 	0x0C80, 0x0C81, 0x0C88, 0x0C8F,
519 	0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2,
521 	0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23,
523 	0x0E40, 0x0E4A,
525 	0x0E60, 0x0E61, 0x0E63, 0x0E68,
527 	0x0E80, 0x0E84, 0x0E88, 0x0E95,
528 	/* GRAS CTX 0 */
529 	0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E,
530 	/* PC CTX 0 */
531 	0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7,
532 	/* VFD CTX 0 */
533 	0x2200, 0x2204, 0x2208, 0x22A9,
535 	0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E,
537 	0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7,
539 	0x2600, 0x2604, 0x2608, 0x26A9,
540 	/* VBIF version 0x20050000*/
541 	0x3000, 0x3007, 0x302C, 0x302C, 0x3030, 0x3030, 0x3034, 0x3036,
542 	0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, 0x3049, 0x3049,
543 	0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, 0x306C, 0x306D,
544 	0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, 0x3098, 0x3098,
545 	0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, 0x30D0, 0x30D0,
546 	0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, 0x3108, 0x3108,
547 	0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, 0x3124, 0x3125,
548 	0x3129, 0x3129, 0x340C, 0x340C, 0x3410, 0x3410,
549 	~0 /* sentinel */
583 		/* Set the default register values; set SW_COLLAPSE to 0 */  in a4xx_pm_resume()
584 		gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);  in a4xx_pm_resume()
590 	return 0;  in a4xx_pm_resume()
603 		gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778001);  in a4xx_pm_suspend()
605 	return 0;  in a4xx_pm_suspend()
613 	return 0;  in a4xx_get_timestamp()
669 	gpu->num_perfcntrs = 0;  in a4xx_gpu_init()
702 	icc_set_bw(gpu->icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);  in a4xx_gpu_init()
703 	icc_set_bw(gpu->ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);  in a4xx_gpu_init()