Lines Matching +full:0 +full:- +full:1023
1 // SPDX-License-Identifier: GPL-2.0-or-later
24 * - OSD1 RGB565/RGB888/xRGB8888 scanout
25 * - RGB conversion to x/cb/cr
26 * - Progressive or Interlace buffer scanout
27 * - OSD1 Commit on Vsync
28 * - HDR OSD matrix for GXL/GXM
32 * - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
33 * - YUV4:2:2 Y0CbY1Cr scanout
34 * - Conversion to YUV 4:4:4 from 4:2:2 input
35 * - Colorkey Alpha matching
36 * - Big endian scanout
37 * - X/Y reverse scanout
38 * - Global alpha setup
39 * - OSD2 support, would need interlace switching on vsync
40 * - OSD1 full scaling to support TV overscan
46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
65 COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
66 COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
93 writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
95 writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
97 writel((m[11] & 0x1fff) << 16, in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
100 writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
102 writel(m[20] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
105 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
115 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_osd_matrix()
116 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_osd_matrix()
117 writel(m[2] & 0xfff, in meson_viu_set_osd_matrix()
118 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_osd_matrix()
119 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_osd_matrix()
120 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01)); in meson_viu_set_osd_matrix()
121 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_osd_matrix()
122 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10)); in meson_viu_set_osd_matrix()
123 writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff), in meson_viu_set_osd_matrix()
124 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12)); in meson_viu_set_osd_matrix()
125 writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), in meson_viu_set_osd_matrix()
126 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21)); in meson_viu_set_osd_matrix()
129 writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff), in meson_viu_set_osd_matrix()
130 priv->io_base + in meson_viu_set_osd_matrix()
132 writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff), in meson_viu_set_osd_matrix()
133 priv->io_base + in meson_viu_set_osd_matrix()
135 writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff), in meson_viu_set_osd_matrix()
136 priv->io_base + in meson_viu_set_osd_matrix()
138 writel(m[17] & 0x1fff, priv->io_base + in meson_viu_set_osd_matrix()
141 writel((m[11] & 0x1fff) << 16, priv->io_base + in meson_viu_set_osd_matrix()
144 writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), in meson_viu_set_osd_matrix()
145 priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_osd_matrix()
146 writel(m[20] & 0xfff, in meson_viu_set_osd_matrix()
147 priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2)); in meson_viu_set_osd_matrix()
150 priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
152 priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
155 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_osd_matrix()
156 priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); in meson_viu_set_osd_matrix()
157 writel_bits_relaxed(BIT(1), 0, in meson_viu_set_osd_matrix()
158 priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); in meson_viu_set_osd_matrix()
163 for (i = 0; i < 5; i++) in meson_viu_set_osd_matrix()
164 writel(((m[i * 2] & 0x1fff) << 16) | in meson_viu_set_osd_matrix()
165 (m[i * 2 + 1] & 0x1fff), priv->io_base + in meson_viu_set_osd_matrix()
168 writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, in meson_viu_set_osd_matrix()
169 priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); in meson_viu_set_osd_matrix()
170 writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, in meson_viu_set_osd_matrix()
171 priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); in meson_viu_set_osd_matrix()
200 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
202 for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) in meson_viu_set_osd_lut()
204 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
206 writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16), in meson_viu_set_osd_lut()
207 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
209 for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) in meson_viu_set_osd_lut()
211 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
213 for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) in meson_viu_set_osd_lut()
215 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
217 writel(b_map[OSD_OETF_LUT_SIZE - 1], in meson_viu_set_osd_lut()
218 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
221 writel_bits_relaxed(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
222 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
224 writel_bits_relaxed(0x7 << 29, 0, in meson_viu_set_osd_lut()
225 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
227 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
229 for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) in meson_viu_set_osd_lut()
231 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
233 writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16), in meson_viu_set_osd_lut()
234 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
236 for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) in meson_viu_set_osd_lut()
238 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
240 for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) in meson_viu_set_osd_lut()
242 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
244 writel(b_map[OSD_EOTF_LUT_SIZE - 1], in meson_viu_set_osd_lut()
245 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
249 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
251 writel_bits_relaxed(7 << 27, 0, in meson_viu_set_osd_lut()
252 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
255 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
261 0x0000, 0x0200, 0x0400, 0x0600,
262 0x0800, 0x0a00, 0x0c00, 0x0e00,
263 0x1000, 0x1200, 0x1400, 0x1600,
264 0x1800, 0x1a00, 0x1c00, 0x1e00,
265 0x2000, 0x2200, 0x2400, 0x2600,
266 0x2800, 0x2a00, 0x2c00, 0x2e00,
267 0x3000, 0x3200, 0x3400, 0x3600,
268 0x3800, 0x3a00, 0x3c00, 0x3e00,
269 0x4000
274 0, 0, 0, 0,
275 0, 32, 64, 96,
283 1023, 1023, 1023, 1023,
284 1023
321 priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_viu_osd1_reset()
323 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_viu_osd1_reset()
327 priv->io_base + _REG(VIU_SW_RESET)); in meson_viu_osd1_reset()
328 writel_bits_relaxed(VIU_SW_RESET_OSD1, 0, in meson_viu_osd1_reset()
329 priv->io_base + _REG(VIU_SW_RESET)); in meson_viu_osd1_reset()
333 priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_viu_osd1_reset()
335 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_viu_osd1_reset()
368 priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); in meson_viu_g12a_enable_osd1_afbc()
370 switch (priv->afbcd.format) { in meson_viu_g12a_enable_osd1_afbc()
383 priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); in meson_viu_g12a_enable_osd1_afbc()
388 priv->io_base + _REG(OSD_PATH_MISC_CTRL)); in meson_viu_g12a_enable_osd1_afbc()
394 writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, 0, in meson_viu_g12a_disable_osd1_afbc()
395 priv->io_base + _REG(OSD_PATH_MISC_CTRL)); in meson_viu_g12a_disable_osd1_afbc()
398 writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN, 0, in meson_viu_g12a_disable_osd1_afbc()
399 priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); in meson_viu_g12a_disable_osd1_afbc()
404 writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x90), in meson_viu_gxm_enable_osd1_afbc()
405 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_viu_gxm_enable_osd1_afbc()
410 writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x00), in meson_viu_gxm_disable_osd1_afbc()
411 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_viu_gxm_disable_osd1_afbc()
419 writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0, in meson_viu_init()
420 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_viu_init()
421 writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0, in meson_viu_init()
422 priv->io_base + _REG(VIU_OSD2_CTRL_STAT)); in meson_viu_init()
444 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_viu_init()
445 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); in meson_viu_init()
448 writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, in meson_viu_init()
449 0xff << OSD_REPLACE_SHIFT, in meson_viu_init()
450 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_viu_init()
451 writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, in meson_viu_init()
452 0xff << OSD_REPLACE_SHIFT, in meson_viu_init()
453 priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); in meson_viu_init()
456 /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/ in meson_viu_init()
457 writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0, in meson_viu_init()
458 priv->io_base + _REG(VIU_MISC_CTRL0)); in meson_viu_init()
459 writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); in meson_viu_init()
461 writel_relaxed(0x00FF00C0, in meson_viu_init()
462 priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE)); in meson_viu_init()
463 writel_relaxed(0x00FF00C0, in meson_viu_init()
464 priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); in meson_viu_init()
467 writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) | in meson_viu_init()
468 VIU_OSD_BLEND_REORDER(1, 0) | in meson_viu_init()
469 VIU_OSD_BLEND_REORDER(2, 0) | in meson_viu_init()
470 VIU_OSD_BLEND_REORDER(3, 0) | in meson_viu_init()
477 priv->io_base + _REG(VIU_OSD_BLEND_CTRL)); in meson_viu_init()
480 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_viu_init()
482 priv->io_base + _REG(OSD2_BLEND_SRC_CTRL)); in meson_viu_init()
483 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_viu_init()
484 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); in meson_viu_init()
485 writel_relaxed(0, in meson_viu_init()
486 priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0)); in meson_viu_init()
487 writel_relaxed(0, in meson_viu_init()
488 priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA)); in meson_viu_init()
490 writel_bits_relaxed(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc), in meson_viu_init()
491 priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_viu_init()
499 priv->viu.osd1_enabled = false; in meson_viu_init()
500 priv->viu.osd1_commit = false; in meson_viu_init()
501 priv->viu.osd1_interlace = false; in meson_viu_init()